Alternatives and similar repositories for riscv-probe

Users that are interested in riscv-probe are comparing it to the libraries listed below

• riscv / riscv-plic-spec
  PLIC Specification
  ☆149Updated last month
• illustris / FreeRTOS-RISCV
  A port of FreeRTOS for the RISC-V ISA
  ☆77Updated 6 years ago
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆280Updated last week
• embench / embench-iot
  The main Embench repository
  ☆292Updated last year
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆159Updated 3 years ago
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆152Updated this week
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆194Updated 3 weeks ago
• riscvarchive / riscv-code-size-reduction
  ☆147Updated last year
• s094392 / riscv-bare-metal
  A RISC-V bare metal example
  ☆51Updated 3 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆233Updated 11 months ago
• riscvarchive / riscv-CMOs
  ☆89Updated last month
• riscvarchive / riscv-eabi-spec
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆27Updated 4 years ago
• riscvarchive / riscv-platform-specs
  RISC-V Profiles and Platform Specification
  ☆114Updated 2 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆200Updated last year
• riscv / riscv-aia
  ☆96Updated last month
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆214Updated last year
• riscv-ovpsim / imperas-riscv-tests
  ☆190Updated last year
• riscvarchive / riscv-binutils-gdb
  RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
  ☆150Updated 3 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆164Updated 5 years ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆89Updated 4 months ago
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆102Updated 4 years ago
• five-embeddev / riscv-scratchpad
  RISC-V Scratchpad
  ☆71Updated 2 years ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆136Updated last week
• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆106Updated 7 years ago
• twilco / riscv-from-scratch
  The code for the RISC-V from scratch blog post series.
  ☆94Updated 5 years ago
• leros-dev / leros
  A Tiny Processor Core
  ☆113Updated 3 months ago
• openrisc / or1200
  OpenRISC 1200 implementation
  ☆172Updated 9 years ago
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆166Updated last month
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 5 months ago