Alternatives and similar repositories for sidechan

Users that are interested in sidechan are comparing it to the libraries listed below

• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆31Updated 8 months ago
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆22Updated 3 years ago
• tomverbeure / intel_jtag_primitive_blog
  How to use the Intel JTAG primitive without using virtual JTAG
  ☆17Updated 3 years ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆38Updated 3 years ago
• mattvenn / logLUTs
  Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.
  ☆21Updated last year
• amaranth-lang / rtl-debugger
  VS Code based debugger for hardware designs in Amaranth or Verilog
  ☆39Updated 7 months ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆49Updated 5 months ago
• litex-hub / litehyperbus
  Small footprint and configurable HyperBus core
  ☆12Updated 3 years ago
• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆39Updated last year
• grayresearch / s4ga
  a small simple slow serial FPGA core
  ☆16Updated 4 years ago
• efabless / caravel-lite
  ☆17Updated 8 months ago
• amaranth-lang / amaranth-stdio
  Industry standard I/O for Amaranth HDL
  ☆28Updated 9 months ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆60Updated last week
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆31Updated 3 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆45Updated 4 months ago
• daveshah1 / ElasticC
  lightweight open HLS for FPGA rapid prototyping
  ☆20Updated 7 years ago
• rob-ng15 / PAWS
  PLEASE MOVE TO PAWSv2
  ☆17Updated 3 years ago
• swetland / os-workshop
  Some materials and sample source for RV32 OS projects.
  ☆22Updated 3 years ago
• GuzTech / shdl6800
  shdl6800: A 6800 processor written in SpinalHDL
  ☆26Updated 5 years ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• lambdaconcept / lambdaUSB
  A configurable USB 2.0 device core
  ☆31Updated 5 years ago
• Wren6991 / ChristmasSoC
  Dual-core RISC-V SoC with JTAG, atomics, SDRAM
  ☆25Updated 3 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆21Updated 7 years ago
• YosysHQ / prjpeppercorn
  Project Peppercorn - GateMate FPGA Bitstream Documentation
  ☆23Updated this week
• mmicko / cross-fpga
  Cross compile FPGA tools
  ☆21Updated 4 years ago
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated 2 months ago
• samlittlewood / caravel_carrier
  Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.
  ☆18Updated 3 years ago
• no2fpga / no2muacm
  Drop In USB CDC ACM core for iCE40 FPGA
  ☆34Updated 3 years ago
• bieganski / mtkcpu
  RISC-V CPU implementation in Amaranth HDL (aka nMigen)
  ☆29Updated 10 months ago