Alternatives and similar repositories for digitaljs_online

Users that are interested in digitaljs_online are comparing it to the libraries listed below

• tilk / yosys2digitaljs
  Export netlists from Yosys to DigitalJS
  ☆51Updated 2 months ago
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆295Updated last week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆216Updated 7 months ago
• ZipCPU / vgasim
  A Video display simulator
  ☆174Updated 5 months ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆158Updated 7 months ago
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆185Updated 3 weeks ago
• Lramseyer / vaporview
  Waveform Viewer Extension for VScode
  ☆281Updated this week
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆311Updated last year
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆136Updated 3 years ago
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆276Updated last year
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆147Updated 5 months ago
• stevehoover / warp-v
  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  ☆241Updated 5 months ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆246Updated last year
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆187Updated this week
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆185Updated 10 months ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆160Updated 3 weeks ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆201Updated last week
• minerva-cpu / minerva
  A 32-bit RISC-V soft processor
  ☆316Updated 3 months ago
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆218Updated last week
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆160Updated last week
• lnis-uofu / SOFA
  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
  ☆142Updated 2 years ago
• dineshannayya / riscduino
  Arduino compatible Risc-V Based SOC
  ☆157Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆121Updated 3 months ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆91Updated 3 weeks ago
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆181Updated 2 weeks ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆302Updated 3 weeks ago
• pieter3d / simview
  ☆85Updated 3 weeks ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆475Updated 2 weeks ago
• SpinalHDL / SpinalWorkshop
  Labs to learn SpinalHDL
  ☆149Updated last year
• SpinalHDL / NaxRiscv
  ☆300Updated this week