Alternatives and similar repositories for digitaljs_online:

Users that are interested in digitaljs_online are comparing it to the libraries listed below

• tilk / yosys2digitaljs
  Export netlists from Yosys to DigitalJS
  ☆48Updated last year
• Lramseyer / vaporview
  Waveform Viewer Extension for VScode
  ☆102Updated last week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆177Updated this week
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆288Updated last year
• pieter3d / simview
  ☆77Updated 11 months ago
• SpinalHDL / NaxRiscv
  ☆275Updated last week
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆170Updated 2 months ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆225Updated 4 months ago
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆280Updated this week
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆153Updated 10 months ago
• ZipCPU / vgasim
  A Video display simulator
  ☆161Updated 7 months ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆306Updated this week
• Nic30 / d3-wave
  D3.js based wave (signal) visualizer
  ☆61Updated last year
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆127Updated last month
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆369Updated last month
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated 11 months ago
• lnis-uofu / SOFA
  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
  ☆136Updated last year
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆390Updated last month
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆209Updated 3 months ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆166Updated 6 months ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆426Updated last week
• wavedrom / vcdrom
  VCD viewer
  ☆84Updated 3 months ago
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆272Updated 10 months ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆145Updated last week
• cirosantilli / vcdvcd
  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
  ☆57Updated 3 months ago
• raczben / fliplot
  HTML & Js based VCD viewer
  ☆60Updated 4 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆126Updated 3 weeks ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆145Updated 3 months ago
• Nic30 / d3-hwschematic
  D3.js and ELK based schematic visualizer
  ☆99Updated 11 months ago