Alternatives and similar repositories for Netlist

Users that are interested in Netlist are comparing it to the libraries listed below

• purdue-onchip / gds2Para
  GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
  ☆121Updated 2 years ago
• KenKundert / psf_utils
  Read Spectre PSF files
  ☆65Updated last week
• dan-fritchman / Hdl21
  Hardware Description Library
  ☆81Updated 3 months ago
• niftylab / laygo2
  LAYout with Gridded Objects v2
  ☆59Updated last month
• bluecheetah / bag
  BAG framework
  ☆41Updated last year
• ashwith / pyMOSChar
  Python port of Prof. Boris Murmann's gm/ID Starter Kit
  ☆54Updated 8 years ago
• Vlsir / Vlsir
  Interchange formats for chip design.
  ☆31Updated 2 months ago
• gmagno / spyci
  A tiny Python package to parse spice raw data files.
  ☆53Updated 2 years ago
• gdsfactory / skywater130
  skywater 130nm pdk
  ☆31Updated this week
• ChrisZonghaoLi / gm_id_gf180mcu
  This repo contains introduction of gm/id method and its application to some OTA design examples.
  ☆18Updated last year
• johnkustin / bandgapReferenceCircuit
  repository for a bandgap voltage reference in SKY130 technology
  ☆38Updated 2 years ago
• AugustUnderground / pyspectre
  Python interface for Cadence Spectre
  ☆15Updated this week
• patrickschulz / openPCells
  Parametric layout generator for digital, analog and mixed-signal integrated circuits
  ☆56Updated this week
• magical-eda / MAGICAL-CIRCUITS
  Circuit release of the MAGICAL project
  ☆35Updated 5 years ago
• dwarning / VA-Models
  Verilog-A simulation models
  ☆78Updated this week
• cascode-labs / virtue
  A Python and SKILL Framework for Cadence Virtuoso
  ☆40Updated last year
• ucb-art / bag
  BAG framework
  ☆30Updated 7 months ago
• dreoilin / pygmid
  A python3 gm/ID starter kit
  ☆51Updated 11 months ago
• ALIGN-analoglayout / AnalogDetailedRouter
  Intel's Analog Detailed Router
  ☆39Updated 6 years ago
• ucb-art / BAG2_cds_ff_mpt
  BAG2 workspace for fake PDK (cds_ff_mpt)
  ☆58Updated 5 years ago
• RTimothyEdwards / netgen
  Netgen complete LVS tool for comparing SPICE or verilog netlists
  ☆121Updated 2 months ago
• ACMmodel / MOSFET_model
  A simple MOSFET model with only 5-DC-parameters for circuit simulation
  ☆45Updated 3 weeks ago
• idea-fasoc / fasoc
  ☆55Updated last year
• christophmuellerorg / spectre_python
  Simple and most probably incomplete parser for spectre netlists
  ☆15Updated 8 years ago
• sgherbst / msdsl
  Automatic generation of real number models from analog circuits
  ☆42Updated last year
• ananthchellappa / SKILL
  Cadence SKILL utilities that have boosted my productivity considerably for 10+ years.
  ☆46Updated last month
• stineje / CharLib
  Open-source repository for a standard-cell library characterizer using complete open-source tools
  ☆35Updated last week
• fsitok / gds3xtrude
  Simple 3D layout viewer for KLayout (Salt package)
  ☆20Updated 6 years ago
• thesourcerer8 / OpenSourceTCAD
  Easy access to OpenSource TCAD Tools
  ☆38Updated 2 years ago
• wulffern / aicex
  Files for Advanced Integrated Circuits
  ☆29Updated 2 months ago