sumukhathrey / Verilog_ASIC_DesignLinks
Verilog for ASIC Design
☆31Updated 4 years ago
Alternatives and similar repositories for Verilog_ASIC_Design
Users that are interested in Verilog_ASIC_Design are comparing it to the libraries listed below
Sorting:
- Verilog RTL Design☆46Updated 4 years ago
- A 2D convolution hardware implementation written in Verilog☆51Updated 4 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆126Updated 3 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆58Updated 2 years ago
- Implementing Different Adder Structures in Verilog☆76Updated 6 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆64Updated last year
- Verilog digital signal processing components☆161Updated 3 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆82Updated 3 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆97Updated 6 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆118Updated 2 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆65Updated last year
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆98Updated last year
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆37Updated 3 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated 2 years ago
- Curriculum for a university course to teach chip design using open source EDA tools☆125Updated 2 years ago
- A simple DDR3 memory controller☆61Updated 2 years ago
- SystemVerilog Tutorial☆185Updated 2 weeks ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆115Updated 5 years ago
- ☆45Updated last year
- Static Timing Analysis Full Course☆63Updated 2 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆175Updated this week
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆66Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆129Updated 2 months ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆52Updated 4 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆30Updated 3 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆67Updated 9 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆67Updated 3 years ago
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆49Updated 6 years ago