Alternatives and similar repositories for Verilog_ASIC_Design:

Users that are interested in Verilog_ASIC_Design are comparing it to the libraries listed below

• ishfaqahmed29 / SerDes
  Verilog RTL Design
  ☆34Updated 3 years ago
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆58Updated last year
• abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
  I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …
  ☆41Updated last year
• AnoushkaTripathi / NASSCOM-VSD-SoC-design-Program
  In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…
  ☆10Updated 8 months ago
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆65Updated 5 years ago
• kerimturak / tcore-rv32imc
  ☆12Updated 3 weeks ago
• sure-trust / VLSI-Project-AXI-to-APB-Bridge
  ☆17Updated last year
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆23Updated last year
• fayizferosh / soc-design-and-planning-nasscom-vsd
  2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…
  ☆19Updated last year
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆42Updated 4 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆65Updated 4 months ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆66Updated 3 years ago
• Danishazmi29 / Verilog-Code-of-Synchronus-FIFO-Design-with-verilog-test-code
  A FIFO or Queue is an array of memory commonly used in hardware to transfer transfer data between two circuits with different clocks. The…
  ☆14Updated 7 years ago
• cepdnaclk / e16-co502-RV32IM-pipeline-implementation-group1
  The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…
  ☆24Updated 3 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆61Updated 3 years ago
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆57Updated 2 years ago
• Kobzon86 / Convolutional-Neural-Network-using-SystemVerilog
  Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
  ☆58Updated 5 months ago
• ivanvig / 2dconv-FPGA
  A 2D convolution hardware implementation written in Verilog
  ☆44Updated 4 years ago
• fayizferosh / yosys-tcl-ui-report
  5 Day TCL begginer to advanced training workshop by VSD
  ☆17Updated last year
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆38Updated 4 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆68Updated last week
• learn-cocotb / tutorial
  Complete tutorial code.
  ☆19Updated 11 months ago
• abdelazeem201 / Cadence-RTL-to-GDSII-Flow
  In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
  ☆57Updated last year
• snbk001 / 100DaysofRTL
  100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…
  ☆34Updated 2 years ago
• manili / VSDBabySoC
  VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
  ☆41Updated 3 years ago
• bol-edu / caravel-soc_fpga-lab
  ☆17Updated 2 weeks ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆85Updated last year
• merldsu / RISCV_Single_Cycle_Core
  This repository contains the design files of RISC-V Single Cycle Core
  ☆42Updated last year
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆44Updated 9 months ago
• yathAg / openroad_vsd_7nmContest
  ☆15Updated 2 years ago