Standalone application based on ADI hdl and no_OS for ANTSDR.
☆23Mar 27, 2025Updated 11 months ago
Alternatives and similar repositories for antsdr_standalone
Users that are interested in antsdr_standalone are comparing it to the libraries listed below
Sorting:
- pynq framework for antsdr☆37May 31, 2024Updated last year
- Repository of antsdr firmware make☆92Feb 10, 2026Updated last month
- This repo contains both the uhd host driver and firmware for microphase antsdr devices.☆93Jan 14, 2025Updated last year
- Testbenches for HDL projects☆22Updated this week
- Generates simple AXI4-lite IP for use in Vivado from register specifications☆15Apr 11, 2025Updated 11 months ago
- Store the openwifi FPGA img (.xsa .ltx) and the related git info☆16Aug 6, 2025Updated 7 months ago
- RFSoC QSFP Data Offload Design with GNU Radio☆26Updated this week
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆37Jun 22, 2023Updated 2 years ago
- Thesis: Custom Filter Designs on the Red Pitaya☆12Jan 8, 2018Updated 8 years ago
- Ubuntu 20.04 Desktop for Ultra96/Ultra96-V2☆11Nov 27, 2021Updated 4 years ago
- HJ212-2017协议C语言实 现，支持协议组包☆12Apr 13, 2023Updated 2 years ago
- IP prototyping in FPGA hardware☆18Aug 28, 2018Updated 7 years ago
- Re-coded Xilinx primitives for Verilator use☆52Jun 24, 2025Updated 8 months ago
- Python Utilities to use Xilinx Vivado Tools from Python Scripts☆22Oct 18, 2020Updated 5 years ago
- UDP and TCP echo servers using lwIP RAW API running on Xilinx Zynq Platform☆12Apr 15, 2014Updated 11 years ago
- A verilog FPGA Interface for AXI4_Lite from Slave side☆11Jun 14, 2020Updated 5 years ago
- IIO AD9361 library for filter design and handling, multi-chip sync, etc.☆101Updated this week
- HDL & FPGA 学习和规范。CC-BY-NC-SA 4.0。☆15Jun 9, 2023Updated 2 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆18Aug 28, 2019Updated 6 years ago
- ☆13May 22, 2015Updated 10 years ago
- Unit testing for cocotb☆11Aug 6, 2023Updated 2 years ago
- Python productivity for RFSoC platforms☆90Oct 31, 2025Updated 4 months ago
- ☆15Jun 7, 2022Updated 3 years ago
- Transmission of HDMI Signals over Spartan 6 - XC6SLX45 . Transmission of High-Definition Multimedia Interface (HDMI) and Digital Visual …☆13Feb 13, 2020Updated 6 years ago
- Using Software Designed Radio to transmit & receive FM signal☆48Apr 2, 2018Updated 7 years ago
- HDL code for a DDS (direct digital synthesizer) with AXI stream interface☆24Apr 16, 2023Updated 2 years ago
- ☆24Apr 12, 2025Updated 11 months ago
- A little demo how to bind an advanced data science algorithms to 4 different languages☆10Nov 6, 2018Updated 7 years ago
- This is the Analog Devices Inc. Yocto/OpenEmbedded layer☆51Oct 29, 2025Updated 4 months ago
- ☆15Dec 1, 2022Updated 3 years ago
- ☆13Mar 2, 2023Updated 3 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Jan 8, 2021Updated 5 years ago
- GigE Vision compatibe video streaming from MIPI-CSI camera with Zybo Z7-10 board☆33Jun 26, 2020Updated 5 years ago
- SDK for FPGA / Linux Instruments☆108Updated this week
- The VD100 development board is based on the Xilinx Versal AI Edge series chip xcve2302 and is designed with a core board and a bottom boa…☆18Jul 9, 2024Updated last year
- SVA examples and demonstration☆18Sep 8, 2020Updated 5 years ago
- ☆21Mar 30, 2023Updated 2 years ago
- Python scripts for KiCad☆11Mar 21, 2016Updated 10 years ago
- All Digital Phase-Locked Loop☆12May 22, 2023Updated 2 years ago