Alternatives and similar repositories for antsdr_standalone

Users that are interested in antsdr_standalone are comparing it to the libraries listed below

• Teddy-van-Jerry / sdr-psk-fpga
  Dual-Mode PSK Transceiver on SDR With FPGA
  ☆41Updated 11 months ago
• Grootzz / AD9361_TX_MSK
  A project demonstrate how to config ad9361 to TX mode and how to transmit MSK
  ☆58Updated 6 years ago
• strath-sdr / rfsoc_ofdm
  PYNQ example of an OFDM Transmitter and Receiver on RFSoC.
  ☆51Updated 2 years ago
• catkira / complex_multiplier
  HDL code for a complex multiplier with AXI stream Interface
  ☆13Updated 2 years ago
• strath-sdr / rfsoc_qsfp_offload
  RFSoC QSFP Data Offload Design with GNU Radio
  ☆23Updated 9 months ago
• yugithub / OFDM-baseband
  Verilog实现OFDM基带
  ☆44Updated 9 years ago
• Xilinx / RFSoC-PYNQ
  Python productivity for RFSoC platforms
  ☆79Updated 2 months ago
• lisliyongming / JESD204B
  通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结
  ☆23Updated 5 years ago
• analogdevicesinc / TransceiverToolbox
  MATLAB toolbox for ADI transceiver products
  ☆63Updated 5 months ago
• phthinh / OFDM_802_11
  IEEE 802.11 OFDM-based transceiver system
  ☆35Updated 7 years ago
• OpenResearchInstitute / dvb_fpga
  RTL implementation of components for DVB-S2
  ☆122Updated 2 years ago
• strath-sdr / rfsoc_qpsk
  PYNQ example of using the RFSoC as a QPSK transceiver.
  ☆107Updated 2 years ago
• Hamid-R-Tanhaei / ZYNQ_ADC_DMA_LWIP
  Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP
  ☆51Updated 4 years ago
• open-sdr / openofdm
  Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
  ☆119Updated 2 months ago
• analogdevicesinc / ad936x-filter-wizard
  MATLAB-based FIR filter design
  ☆60Updated last year
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆30Updated 6 years ago
• phthinh / OFDM_802_16
  IEEE 802.16 OFDM-based transceiver system
  ☆26Updated 6 years ago
• MicroPhase / antsdr-pynq
  pynq framework for antsdr
  ☆36Updated last year
• dshekhalev / FEC
  FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)
  ☆118Updated last year
• strath-sdr / rfsoc_frequency_planner
  An RFSoC Frequency Planner developed using Python.
  ☆30Updated 2 years ago
• jfoshea / Viterbi-Decoder-in-Verilog
  An efficient implementation of the Viterbi decoding algorithm in Verilog
  ☆54Updated last year
• cjhonlyone / ADC-lvds
  Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS
  ☆54Updated 2 years ago
• regymm / PYNQSDR
  PYNQ-Z1 + AD936X openwifi capable SDR platform
  ☆114Updated 2 months ago
• Lcrypto / FEC-Archive-Verilog
  Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…
  ☆76Updated 2 years ago
• MicroPhase / antsdr-fw
  ANTSDR Firmware
  ☆136Updated 2 years ago
• daveshah1 / RFToolSDR
  AD9361 based USB3 SDR
  ☆116Updated 7 years ago
• Xilinx / RFSoC2x2-PYNQ
  RFSoC2x2 board repo for PYNQ
  ☆17Updated 2 years ago
• strath-sdr / rfsoc_sam
  RFSoC Spectrum Analyser Module on PYNQ.
  ☆84Updated last year
• IMDEANetworksWNG / MIMORPH
  ☆28Updated last year
• MeowLucian / SDR_FM_Radio
  Using Software Designed Radio to transmit & receive FM signal
  ☆45Updated 7 years ago