Standalone application based on ADI hdl and no_OS for ANTSDR.
☆26Mar 27, 2025Updated last year
Alternatives and similar repositories for antsdr_standalone
Users that are interested in antsdr_standalone are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- some gnu radio demo for antsdr☆19Nov 25, 2021Updated 4 years ago
- Repository of antsdr firmware make☆97Feb 10, 2026Updated 2 months ago
- This repo contains both the uhd host driver and firmware for microphase antsdr devices.☆94Jan 14, 2025Updated last year
- Testbenches for HDL projects☆23Apr 20, 2026Updated last week
- Generates simple AXI4-lite IP for use in Vivado from register specifications☆16Apr 11, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Store the openwifi FPGA img (.xsa .ltx) and the related git info☆17Aug 6, 2025Updated 8 months ago
- RFSoC QSFP Data Offload Design with GNU Radio☆28Mar 16, 2026Updated last month
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆38Jun 22, 2023Updated 2 years ago
- Thesis: Custom Filter Designs on the Red Pitaya☆12Jan 8, 2018Updated 8 years ago
- Ubuntu 20.04 Desktop for Ultra96/Ultra96-V2☆11Nov 27, 2021Updated 4 years ago
- HJ212-2017协议C语言实现,支持协议组包☆12Apr 13, 2023Updated 3 years ago
- Re-coded Xilinx primitives for Verilator use☆53Jun 24, 2025Updated 10 months ago
- FAT32 images☆22Jan 8, 2020Updated 6 years ago
- Python Utilities to use Xilinx Vivado Tools from Python Scripts☆22Oct 18, 2020Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- UDP and TCP echo servers using lwIP RAW API running on Xilinx Zynq Platform☆12Apr 15, 2014Updated 12 years ago
- A verilog FPGA Interface for AXI4_Lite from Slave side☆11Jun 14, 2020Updated 5 years ago
- Example applications for UHD/RFNoC☆19Mar 8, 2022Updated 4 years ago
- HDL & FPGA 学习和规范。CC-BY-NC-SA 4.0。☆16Jun 9, 2023Updated 2 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆18Aug 28, 2019Updated 6 years ago
- ☆13May 22, 2015Updated 10 years ago
- Unit testing for cocotb☆11Aug 6, 2023Updated 2 years ago
- Python productivity for RFSoC platforms☆91Oct 31, 2025Updated 6 months ago
- ☆15Jun 7, 2022Updated 3 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Transmission of HDMI Signals over Spartan 6 - XC6SLX45 . Transmission of High-Definition Multimedia Interface (HDMI) and Digital Visual …☆13Feb 13, 2020Updated 6 years ago
- HDL code for a DDS (direct digital synthesizer) with AXI stream interface☆24Apr 16, 2023Updated 3 years ago
- Using Software Designed Radio to transmit & receive FM signal☆49Apr 2, 2018Updated 8 years ago
- ☆24Apr 12, 2025Updated last year
- A little demo how to bind an advanced data science algorithms to 4 different languages☆10Nov 6, 2018Updated 7 years ago
- This is the Analog Devices Inc. Yocto/OpenEmbedded layer☆52Oct 29, 2025Updated 6 months ago
- SDIO Device Verilog Core☆24Jul 25, 2018Updated 7 years ago
- ☆15Dec 1, 2022Updated 3 years ago
- ☆12Oct 8, 2020Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆13Mar 2, 2023Updated 3 years ago
- Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.☆132Feb 24, 2026Updated 2 months ago
- GigE Vision compatibe video streaming from MIPI-CSI camera with Zybo Z7-10 board☆33Jun 26, 2020Updated 5 years ago
- SDK for FPGA / Linux Instruments☆109Updated this week
- The VD100 development board is based on the Xilinx Versal AI Edge series chip xcve2302 and is designed with a core board and a bottom boa…☆19Jul 9, 2024Updated last year
- Repository for FPGA projects☆66Dec 1, 2025Updated 5 months ago
- SVA examples and demonstration☆18Sep 8, 2020Updated 5 years ago