Standalone application based on ADI hdl and no_OS for ANTSDR.
☆29Mar 27, 2025Updated last year
Alternatives and similar repositories for antsdr_standalone
Users that are interested in antsdr_standalone are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- pynq framework for antsdr☆37May 31, 2024Updated 2 years ago
- some gnu radio demo for antsdr☆19Nov 25, 2021Updated 4 years ago
- Repository of antsdr firmware make☆101Apr 30, 2026Updated 2 months ago
- Testbenches for HDL projects☆23Jun 17, 2026Updated 2 weeks ago
- Generates simple AXI4-lite IP for use in Vivado from register specifications☆16Apr 11, 2025Updated last year
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Store the openwifi FPGA img (.xsa .ltx) and the related git info☆18Aug 6, 2025Updated 10 months ago
- RFSoC QSFP Data Offload Design with GNU Radio☆30Mar 16, 2026Updated 3 months ago
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆40Jun 22, 2023Updated 3 years ago
- Ubuntu 20.04 Desktop for Ultra96/Ultra96-V2☆11Nov 27, 2021Updated 4 years ago
- Re-coded Xilinx primitives for Verilator use☆54Jun 24, 2025Updated last year
- FAT32 images☆22Jan 8, 2020Updated 6 years ago
- Python Utilities to use Xilinx Vivado Tools from Python Scripts☆22Oct 18, 2020Updated 5 years ago
- A verilog FPGA Interface for AXI4_Lite from Slave side☆11Jun 14, 2020Updated 6 years ago
- IIO AD9361 library for filter design and handling, multi-chip sync, etc.☆105Updated this week
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Example applications for UHD/RFNoC☆20Mar 8, 2022Updated 4 years ago
- HDL & FPGA 学习和规范。CC-BY-NC-SA 4.0。☆15Jun 9, 2023Updated 3 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆18Aug 28, 2019Updated 6 years ago
- ☆13May 22, 2015Updated 11 years ago
- HDL code for a complex multiplier with AXI stream interface☆17Mar 18, 2026Updated 3 months ago
- Unit testing for cocotb☆11Aug 6, 2023Updated 2 years ago
- Python productivity for RFSoC platforms☆97Jun 11, 2026Updated 2 weeks ago
- ☆15Jun 7, 2022Updated 4 years ago
- Transmission of HDMI Signals over Spartan 6 - XC6SLX45 . Transmission of High-Definition Multimedia Interface (HDMI) and Digital Visual …☆13Feb 13, 2020Updated 6 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- HDL code for a DDS (direct digital synthesizer) with AXI stream interface☆25Apr 16, 2023Updated 3 years ago
- Using Software Designed Radio to transmit & receive FM signal☆49Apr 2, 2018Updated 8 years ago
- ☆24Apr 12, 2025Updated last year
- A little demo how to bind an advanced data science algorithms to 4 different languages☆10Nov 6, 2018Updated 7 years ago
- This is the Analog Devices Inc. Yocto/OpenEmbedded layer☆53Jun 12, 2026Updated 2 weeks ago
- SDIO Device Verilog Core☆24Jul 25, 2018Updated 7 years ago
- ☆15Dec 1, 2022Updated 3 years ago
- ☆12Oct 8, 2020Updated 5 years ago
- ☆13Mar 2, 2023Updated 3 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Jan 8, 2021Updated 5 years ago
- Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.☆132Feb 24, 2026Updated 4 months ago
- GigE Vision compatibe video streaming from MIPI-CSI camera with Zybo Z7-10 board☆36Jun 26, 2020Updated 6 years ago
- The VD100 development board is based on the Xilinx Versal AI Edge series chip xcve2302 and is designed with a core board and a bottom boa…☆20Jul 9, 2024Updated last year
- SDK for FPGA / Linux Instruments☆110May 21, 2026Updated last month
- Repository for FPGA projects☆72Dec 1, 2025Updated 7 months ago
- SVA examples and demonstration☆18Sep 8, 2020Updated 5 years ago