Alternatives and similar repositories for vls

Users that are interested in vls are comparing it to the libraries listed below

• imc-trading / svlangserver
  ☆126Updated 3 weeks ago
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆187Updated last week
• thomasrussellmurphy / istyle-verilog-formatter
  Open source implementation of a Verilog formatter
  ☆183Updated 3 years ago
• WeiChungWu / vim-SystemVerilog
  SystemVerilog syntax highlight/indent support in vim
  ☆51Updated last year
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆113Updated last year
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆145Updated 9 months ago
• jmcneal / verilog-support
  Edit SystemVerilog files (and UVM files) in Vim/gVim
  ☆30Updated last year
• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆218Updated last year
• vhda / verilog_systemverilog.vim
  Verilog/SystemVerilog Syntax and Omni-completion
  ☆411Updated last year
• dalance / svls
  SystemVerilog language server
  ☆553Updated last week
• zhuzhzh / verilog_emacsauto.vim
  verilog filetype plugin to enable emacs verilog-mode autos
  ☆25Updated 3 years ago
• dalance / svlint
  SystemVerilog linter
  ☆370Updated last month
• antoinemadec / vim-verilog-instance
  verilog_instance.vim: create instantiation of ports from port declaration
  ☆30Updated 2 years ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆65Updated 10 months ago
• AndrewNolte / vscode-system-verilog
  SystemVerilog/Verilog support for vscode using Ctags
  ☆37Updated 2 months ago
• dalance / svls-vscode
  SystemVerilog language server client for Visual Studio Code
  ☆23Updated 2 years ago
• subbdue / systemverilog.io
  Code used in
  ☆198Updated 8 years ago
• zion-group / VerilogCodingStyle
  ☆65Updated 5 years ago
• mshr-h / vscode-verilog-hdl-support
  HDL support for VS Code
  ☆343Updated this week
• nachumk / systemverilog.vim
  SystemVerilog vim scripts
  ☆69Updated 2 years ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆72Updated last year
• gmlarumbe / tree-sitter-systemverilog
  SystemVerilog tree-sitter grammar
  ☆42Updated last month
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆430Updated 3 months ago
• raczben / fliplot
  HTML & Js based VCD viewer
  ☆65Updated 4 months ago
• dpretet / svut
  SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
  ☆79Updated last year
• TheClams / SystemVerilog
  SystemVerilog plugin for Sublime Text
  ☆49Updated 2 months ago
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆454Updated last month
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆238Updated 3 months ago
• suzizecat / slang-lsp-tools
  Tools based upon slang for language server purpose
  ☆20Updated this week
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆255Updated 10 months ago