wegul / EDMLinks
An EDM-enabled PHY + a rack-level network simulator
☆12Updated 9 months ago
Alternatives and similar repositories for EDM
Users that are interested in EDM are comparing it to the libraries listed below
Sorting:
- A Programmable Hardware Architecture for Network Transport Logic☆35Updated 3 years ago
- TRAGEN: A Synthetic Trace Generator for Realistic Cache Simulations☆19Updated last year
- ☆14Updated 2 years ago
- Clio, ASPLOS'22.☆78Updated 3 years ago
- An infrastructure for inline acceleration of network applications☆30Updated 3 years ago
- RPCNIC: A High-Performance and Reconfigurable PCIe-attached RPC Accelerator [HPCA2025]☆11Updated 9 months ago
- Ensō is a high-performance streaming interface for NIC-application communication.☆75Updated 3 weeks ago
- ☆29Updated 2 years ago
- Flexible, high-performance TCP offload to SmartNICs using fine-grained parallelism☆58Updated 3 years ago
- Overcoming the IOTLB Wall for Multi-100-Gbps Linux-based Networking☆22Updated 2 years ago
- ☆31Updated 4 years ago
- CXLMemSim: A pure software simulated CXL.mem for performance characterization☆168Updated this week
- A Fast, Scalable and Programmable Packet Scheduler in Hardware☆38Updated 6 years ago
- This is the respository that holds the artifacts of MICRO'23 -- Demystifying CXL Memory with True CXL-Ready Systems and CXL Memory Device…☆50Updated last year
- ☆24Updated 4 years ago
- CXL-DMSim: A Full-System CXL Disaggregated Memory Simulator With Comprehensive Silicon Validation☆92Updated 2 weeks ago
- An FPGA-based full-stack in-storage computing system.☆38Updated 4 years ago
- Demystifying Datapath Accelerator Enhanced Off-path SmartNIC [ICNP24]☆44Updated 9 months ago
- The Artifact of NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering☆57Updated last year
- IRN's packet processing logic synthesized using Xilinx Vivado HLS☆23Updated 6 years ago
- ☆72Updated 2 years ago
- HW/SW co-designed end-host RPC stack☆20Updated 3 years ago
- An Agile Chisel-Based SoC Design Framework☆26Updated 3 years ago
- ☆109Updated 2 years ago
- PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing☆104Updated 2 years ago
- ☆17Updated last year
- Pin based tool for simulation of rack-scale disaggregated memory systems☆29Updated 6 months ago
- Arbitrary offloads for RDMA NICs☆97Updated 3 years ago
- FpgaNIC is an FPGA-based Versatile 100Gb SmartNIC for GPUs [ATC 22]☆132Updated 2 years ago
- A rust-based benchmark for BlueField SmartNICs.☆29Updated 2 years ago