Anjali-287 / SPI-Interface
UVM Testbench to verify serial transmission of data between SPI master and slave
☆42Updated 4 years ago
Alternatives and similar repositories for SPI-Interface:
Users that are interested in SPI-Interface are comparing it to the libraries listed below
- Verification IP for APB protocol☆59Updated 4 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆85Updated last year
- Verification IP for I2C protocol☆41Updated 3 years ago
- Verification IP for SPI protocol☆17Updated 4 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆24Updated 2 years ago
- UVM testbench environment consisting of an APB driver, high level SPI controller model, and SPI verification testbench based upon an LPC2…☆8Updated 2 months ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆30Updated 2 years ago
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆38Updated 4 years ago
- SystemVerilog UVM testbench example☆30Updated 10 months ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆30Updated 4 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆58Updated last year
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆48Updated 4 years ago
- a very simple risc_cpu verification demo with uvm☆22Updated 5 years ago
- UART design in SV and verification using UVM and SV☆40Updated 5 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆17Updated 3 years ago
- AHB-APB UVM Verification Environment☆17Updated 9 years ago
- ☆19Updated 3 years ago
- Verification IP for APB protocol☆26Updated 4 years ago
- UVM AHB VIP☆80Updated 3 months ago
- generate UVM testbench using python☆27Updated 6 years ago
- ☆40Updated 3 years ago
- Sample UVM code for axi ram dut☆31Updated 3 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆56Updated 2 years ago
- AXI Interconnect☆47Updated 3 years ago
- UVM Testbench For SystemVerilog Combinator Implementation☆53Updated 8 years ago
- Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…☆27Updated 6 years ago
- VIP for AXI Protocol☆122Updated 2 years ago
- ☆38Updated last year
- Master and Slave made using AMBA AXI4 Lite protocol.