sifive / benchmark-coremark
CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcrontrollers (MCU).
☆10Updated 4 years ago
Alternatives and similar repositories for benchmark-coremark:
Users that are interested in benchmark-coremark are comparing it to the libraries listed below
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆26Updated 5 years ago
- A Rocket-based RISC-V superscalar in-order core☆29Updated 2 weeks ago
- A fault-injection framework using Chisel and FIRRTL☆34Updated 2 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆43Updated 4 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated last year
- SCARV: a side-channel hardened RISC-V platform☆24Updated 2 years ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆34Updated 3 years ago
- RISC-V Virtual Prototype☆40Updated 3 years ago
- Chisel HDL example applications☆30Updated 2 years ago
- Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program☆30Updated 2 years ago
- Chisel Cheatsheet☆32Updated last year
- Original RISC-V 1.0 implementation. Not supported.☆41Updated 6 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆23Updated 5 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- A DMA Controller for RISCV CPUs☆14Updated 9 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆38Updated 2 months ago
- Documentation for the BOOM processor☆47Updated 7 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆52Updated 4 years ago
- ☆27Updated 2 months ago
- ☆13Updated 4 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆79Updated 4 months ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆20Updated last week
- ☆33Updated 2 years ago
- ☆11Updated 3 years ago
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆19Updated 11 months ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆23Updated 2 years ago
- An example of on-boarding a PIO block in with duh and wake☆12Updated 4 years ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆33Updated 3 weeks ago