Alternatives and similar repositories for Introduction-to-SoC-Design-Education-Kit

Users that are interested in Introduction-to-SoC-Design-Education-Kit are comparing it to the libraries listed below

• arm-university / Advanced-System-on-Chip-Design-Education-Kit
  Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…
  ☆113Updated 2 months ago
• arm-university / VLSI-Fundamentals-Education-Kit
  Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …
  ☆264Updated 2 months ago
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆164Updated 3 months ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆104Updated last year
• amradel2020 / vlsi_linkedin_index
  This repo provide an index of VLSI content creators and their materials
  ☆156Updated last year
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆143Updated 4 years ago
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆79Updated last year
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆108Updated this week
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆140Updated 6 years ago
• mikeroyal / Verilog-SystemVerilog-Guide
  Verilog/SystemVerilog Guide
  ☆72Updated last year
• Kobzon86 / Convolutional-Neural-Network-using-SystemVerilog
  Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
  ☆63Updated 9 months ago
• merldsu / RISCV_Single_Cycle_Core
  This repository contains the design files of RISC-V Single Cycle Core
  ☆52Updated last year
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆150Updated last year
• arm-university / System-on-Chip-Design-with-Arm-Cortex-M-Processors
  A reference book on System-on-Chip Design
  ☆34Updated 2 months ago
• rajdeep66 / edaBundle_whyRD
  opensource EDA tool flor VLSI design
  ☆33Updated last year
• FPGADude / Digital-Design
  Verilog HDL files
  ☆149Updated last year
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆65Updated 2 years ago
• D-curs-D / Inverter-design-and-analysis-using-sky130pdk
  Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools
  ☆115Updated 3 years ago
• RClabiisc / I2SRV32-S-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆30Updated 3 years ago
• raysalemi / Python4RTLVerification
  ☆163Updated 2 years ago
• efabless / chipcraft---mest-course
  ☆36Updated last month
• Fraunhofer-IMS / airisc_core_complex
  Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
  ☆96Updated 2 months ago
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆119Updated 4 years ago
• stevehoover / RISC-V_MYTH_Workshop
  Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop
  ☆93Updated 5 months ago
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆89Updated 2 years ago
• kerimturak / tcore-rv32imc
  ☆12Updated 4 months ago
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆81Updated 4 months ago
• tscheipel / HaDes-V
  HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…
  ☆79Updated 2 months ago
• phoeniX-Digital-Design / phoeniX
  A Reconfigurable RISC-V Core for Approximate Computing
  ☆125Updated 2 months ago
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆76Updated 2 months ago