pheaver / netlist-verilogLinks
Netlist and Verilog Haskell Package
☆18Updated 14 years ago
Alternatives and similar repositories for netlist-verilog
Users that are interested in netlist-verilog are comparing it to the libraries listed below
Sorting:
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Updated 9 years ago
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Updated 8 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆37Updated 4 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- Collection of test cases for Yosys☆17Updated 3 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- RISC-V BSV Specification☆21Updated 5 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- OpenRISC processor IP core based on Tomasulo algorithm☆33Updated 3 years ago
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆19Updated last year
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- Useful utilities for BAR projects☆32Updated last year
- A scala based simulator for circuits described by a LoFirrtl file☆49Updated 2 years ago
- A coverage library for Chisel designs☆11Updated 5 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆147Updated last month
- ABC: System for Sequential Logic Synthesis and Formal Verification☆29Updated last month
- ☆23Updated 5 months ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆37Updated 6 months ago
- Mutation Cover with Yosys (MCY)☆87Updated this week
- Hardware implementation of the SipHash short-inout PRF☆17Updated 6 months ago
- FGPU is a soft GPU architecture general purpose computing☆60Updated 4 years ago
- FPGA Assembly (FASM) Parser and Generator☆96Updated 3 years ago
- A Verilog parser for Haskell.☆36Updated 4 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- ☆56Updated 3 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 5 years ago