pheaver / netlist-verilog
Netlist and Verilog Haskell Package
☆18Updated 14 years ago
Alternatives and similar repositories for netlist-verilog:
Users that are interested in netlist-verilog are comparing it to the libraries listed below
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Updated 8 years ago
- AXI X-Bar☆19Updated 4 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated last year
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Updated 7 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆21Updated last month
- SCARV: a side-channel hardened RISC-V platform☆24Updated 2 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 5 years ago
- Multi-threaded 32-bit embedded core family.☆24Updated 12 years ago
- A Verilog Synthesis Regression Test☆35Updated 10 months ago
- A Verilog parser for Haskell.☆34Updated 3 years ago
- Useful utilities for BAR projects☆30Updated last year
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆33Updated this week
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- Open Processor Architecture☆26Updated 8 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆25Updated 4 years ago
- Mutation Cover with Yosys (MCY)☆79Updated last week
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆27Updated last week
- 🔁 elastic circuit toolchain☆30Updated last month
- A scala based simulator for circuits described by a LoFirrtl file☆47Updated 2 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated last year
- ☆22Updated last year
- ☆52Updated 2 years ago
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆20Updated 5 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆35Updated 3 years ago
- RISC-V BSV Specification☆18Updated 5 years ago