pheaver / netlist-verilogLinks
Netlist and Verilog Haskell Package
☆18Updated 15 years ago
Alternatives and similar repositories for netlist-verilog
Users that are interested in netlist-verilog are comparing it to the libraries listed below
Sorting:
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Updated 9 years ago
- A Verilog Synthesis Regression Test☆37Updated last week
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆38Updated 4 years ago
- Collection of test cases for Yosys☆17Updated 4 years ago
- Mutation Cover with Yosys (MCY)☆90Updated 2 weeks ago
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Updated 8 years ago
- A scala based simulator for circuits described by a LoFirrtl file☆49Updated 3 years ago
- OpenRISC processor IP core based on Tomasulo algorithm☆35Updated 3 years ago
- Multi-threaded 32-bit embedded core family.☆24Updated 13 years ago
- Example of how to use UVM with Verilator☆33Updated last month
- ABC: System for Sequential Logic Synthesis and Formal Verification☆31Updated last week
- A place to share libraries and utilities that don't belong in the core bsc repo☆38Updated 2 weeks ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- A coverage library for Chisel designs☆11Updated 5 years ago
- ☆18Updated 5 years ago
- 🔁 elastic circuit toolchain☆32Updated last year
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆32Updated 4 years ago
- Hardware Formal Verification☆17Updated 5 years ago
- ☆59Updated 3 years ago
- Block-diagram style digital logic visualizer☆23Updated 10 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Updated 5 years ago
- Hardware implementation of the SipHash short-inout PRF☆17Updated 9 months ago
- Iodine: Verifying Constant-Time Execution of Hardware☆15Updated 4 years ago
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆24Updated 6 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆51Updated 10 years ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- A library and command-line tool for querying a Verilog netlist.☆29Updated 3 years ago
- RISC-V BSV Specification☆23Updated 6 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month