A 32-bit MIPS processor used Altera Quartus II with Verilog.
☆28Sep 20, 2018Updated 7 years ago
Alternatives and similar repositories for 32-bit-MIPS-Processor
Users that are interested in 32-bit-MIPS-Processor are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A verilog implementation of MIPS ISA.☆20Jul 7, 2019Updated 7 years ago
- NoC based MPSoC☆11Jul 17, 2014Updated 12 years ago
- A implementation of a 32-bit single cycle MIPS processor in Verilog.☆22Nov 23, 2020Updated 5 years ago
- Super scalar Processor design☆21Sep 7, 2014Updated 11 years ago
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- This repository contains the models and training scripts used in the papers: "Quantizing Spiking Neural Networks with Integers" (ICONS 20…☆13Oct 20, 2020Updated 5 years ago
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 5 years ago
- Implements a simple UVM based testbench for a simple memory DUT.☆12Oct 26, 2019Updated 6 years ago
- Verilog implementation of 74181 ALU chip☆12Oct 8, 2017Updated 8 years ago
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 7 years ago
- An introduction to integrated circuit design with Verilog and the Papilio Pro development board.☆15Jan 5, 2025Updated last year
- Pipelined MIPS architecture created in Verilog. Includes data forwarding and hazard detection.☆16Apr 1, 2018Updated 8 years ago
- The Subutai™ Router open hardware project sources.☆16Oct 2, 2017Updated 8 years ago
- Course project of Computer Architecture, designed by single-cycle datapath. The verilog code could be completely compiled by Quartus II.☆31Feb 14, 2021Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher☆17Feb 27, 2024Updated 2 years ago
- Practices related to the fundamental level of the programming language Verilog.☆13Jan 16, 2023Updated 3 years ago
- Parallel Array of Simple Cores. Multicore processor.☆101May 16, 2019Updated 7 years ago
- Synthesis minecraft redstone schemes from verilog☆18Sep 20, 2018Updated 7 years ago
- 5-stage pipelined 32-bit MIPS microprocessor in Verilog☆146Apr 3, 2020Updated 6 years ago
- The aoR3000 is a MIPS R3000A compatible core capable of booting the Linux kernel version 3.16 in about 3 seconds and with a rating of 48.…☆47Aug 11, 2014Updated 12 years ago
- This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator☆18Apr 12, 2020Updated 6 years ago
- Create tiny ML systems for on-device learning.☆19Jul 14, 2021Updated 5 years ago
- AXI4-Stream FIR filter IP☆20Nov 4, 2022Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆22Feb 4, 2025Updated last year
- Resources for the book "Finite Difference Computing with Exponential Decay Models" by H. P. Langtangen☆17Apr 25, 2020Updated 6 years ago