sevvalmehder / 32-bit-MIPS-Processor
A 32-bit MIPS processor used Altera Quartus II with Verilog.
☆25Updated 6 years ago
Related projects: ⓘ
- 256-bit vector processor based on the RISC-V vector (V) extension☆26Updated 3 years ago
- A simple implementation of a UART modem in Verilog.☆95Updated 2 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆96Updated 4 years ago
- An open source CPU design and verification platform for academia☆87Updated 4 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆47Updated 7 years ago
- RISC V core implementation using Verilog.☆23Updated 3 years ago
- Implementing Different Adder Structures in Verilog☆54Updated 5 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆37Updated 3 years ago
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆117Updated 2 years ago
- Design consists of a 32-bit MIPS superscalar pipeline processor in functional Verilog. Runs a cache based memory system, a branch predict…☆12Updated 6 years ago
- Mathematical Functions in Verilog☆82Updated 3 years ago
- A implementation of a 32-bit single cycle MIPS processor in Verilog.☆18Updated 3 years ago
- IP operations in verilog (simulation and implementation on ice40)☆52Updated 4 years ago
- IC implementation of TPU☆84Updated 4 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆57Updated 7 years ago
- Learn about image processing with an FPGA. Video lectures explain algorithm and implementation of lane detection for automotive driving. …☆31Updated 4 months ago
- Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.☆26Updated 4 years ago
- HW and SW based implementation of Canny Edge Detection Algorithm.☆12Updated 6 years ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆75Updated 3 years ago
- Generic FIFO implementation with optional FWFT☆53Updated 4 years ago
- This repository contains some introductory level review about learning about FPGA Design including some tutorials, links to websites and …☆27Updated 3 months ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆57Updated 4 years ago
- This repository contains source code for past labs and projects involving FPGA and Verilog based designs☆101Updated 4 years ago
- Parallel Array of Simple Cores. Multicore processor.☆92Updated 5 years ago
- ☆23Updated 4 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆109Updated 4 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆59Updated 9 months ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆24Updated 3 years ago
- ☆34Updated 7 months ago
- Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer☆25Updated 2 years ago