Alternatives and similar repositories for 32-bit-MIPS-Processor:

Users that are interested in 32-bit-MIPS-Processor are comparing it to the libraries listed below

• tharunchitipolu / Dadda-Multiplier-using-CSA
  Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
  ☆34Updated 8 months ago
• martinriis / RISC-V-Vector-Processor
  256-bit vector processor based on the RISC-V vector (V) extension
  ☆28Updated 3 years ago
• mihir8181 / VerilogHDL-Codes
  Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.
  ☆34Updated 5 years ago
• spider-tronix / VLSI
  RISC V core implementation using Verilog.
  ☆26Updated 3 years ago
• tianrenz2 / Single-Cycle-Processor
  Single-Cycle RISC-V Processor in systemverylog
  ☆20Updated 5 years ago
• leo47007 / TPU-Tensor-Processing-Unit
  IC implementation of TPU
  ☆98Updated 5 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆63Updated last week
• 4a1c0 / RV32i-Verilog
  Simple RiscV core for academic purpose.
  ☆22Updated 4 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆39Updated last year
• shaneleonard / neural-hardware
  Verilog library for implementing neural networks.
  ☆26Updated 10 years ago
• emilbiju / emil-risc-v
  32 bit RISC-V CPU implementation in Verilog
  ☆27Updated 3 years ago
• djzenma / RV32IC-CPU
  Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.
  ☆15Updated 4 years ago
• vinayrayapati / iiitb_rv32i
  ☆13Updated 2 years ago
• SimpleCPU / SimpleCPU
  An open source CPU design and verification platform for academia
  ☆95Updated 4 years ago
• avashist003 / SystemVerilog_Design_Verification
  Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog
  ☆24Updated 2 years ago
• ljgibbslf / basic_cache_core
  ☆25Updated 4 years ago
• freecores / sgmii
  SGMII
  ☆10Updated 10 years ago
• pontazaricardo / Verilog_Calculator_Matrix_Multiplication
  This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
  ☆50Updated 7 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆55Updated 4 years ago
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆63Updated 5 years ago
• freecores / robust_axi2apb
  Generic AXI to APB bridge
  ☆12Updated 10 years ago
• ahegazy / mips-cpu
  A verilog implementation of MIPS ISA.
  ☆17Updated 5 years ago
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆55Updated 5 years ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆44Updated last month
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• rajshadow / 4-way-set-associative-cache-verilog
  Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy
  ☆40Updated 8 years ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆119Updated 3 years ago
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆61Updated 3 months ago
• ATaylorCEngFIET / Getting-to-Know-Vivado
  Source files for Getting to Know Vivado course
  ☆19Updated 4 years ago
• neeraj1397 / Physical-Design-With-OpenLANE-and-SKY130
  This repository contains all the information studied and created during the [Advanced Physical Design Using OpenLANE / SKY130](https://ww…
  ☆16Updated 2 years ago