diadatp / mips_cpuLinks
A implementation of a 32-bit single cycle MIPS processor in Verilog.
☆20Updated 4 years ago
Alternatives and similar repositories for mips_cpu
Users that are interested in mips_cpu are comparing it to the libraries listed below
Sorting:
- ☆19Updated last month
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 10 months ago
- ☆43Updated 3 years ago
- Completed LDO Design for Skywaters 130nm☆16Updated 2 years ago
- Various low power labs using sky130☆13Updated 4 years ago
- To design test bench of the APB protocol☆17Updated 4 years ago
- Simple implementation of I2C interface written on Verilog and SystemC☆44Updated 8 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆47Updated 6 months ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆15Updated 3 years ago
- SGMII☆13Updated 11 years ago
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆14Updated 6 months ago
- ☆40Updated last year
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆14Updated 3 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆30Updated last year
- Simple strutured VERILOG netlist to SPICE netlist translator☆22Updated 3 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- ☆13Updated last year
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- A simple DDR3 memory controller☆60Updated 2 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆49Updated 3 years ago
- Python Tool for UVM Testbench Generation☆54Updated last year
- ☆15Updated 3 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Updated 2 years ago
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆21Updated 3 years ago
- Open source ISS and logic RISC-V 32 bit project☆58Updated last week
- This repo contain the PY-UVM Framework for different RISC-V Cores☆32Updated 2 years ago
- Verilog RTL Design☆44Updated 4 years ago
- Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns☆14Updated 4 years ago