JeffDeCola / my-verilog-examples
A place to keep my synthesizable verilog examples.
☆32Updated this week
Alternatives and similar repositories for my-verilog-examples:
Users that are interested in my-verilog-examples are comparing it to the libraries listed below
- An open source, parameterized SystemVerilog digital hardware IP library☆24Updated 7 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆62Updated 4 years ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆55Updated last year
- Open source ISS and logic RISC-V 32 bit project☆41Updated last month
- 256-bit vector processor based on the RISC-V vector (V) extension☆28Updated 3 years ago
- Open Source PHY v2☆26Updated 8 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆57Updated last month
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆20Updated 5 years ago
- ☆17Updated this week
- Xilinx AXI VIP example of use☆32Updated 3 years ago
- Introductory course into static timing analysis (STA).☆78Updated 2 months ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆22Updated 6 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 2 years ago
- ☆40Updated 2 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆24Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆61Updated 3 weeks ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆23Updated 2 years ago
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆43Updated 4 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆25Updated 3 months ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆17Updated last year
- General Purpose AXI Direct Memory Access☆48Updated 8 months ago
- Repository gathering basic modules for CDC purpose☆51Updated 5 years ago
- ☆81Updated last year
- Python Tool for UVM Testbench Generation☆50Updated 8 months ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆40Updated 3 years ago
- Announcements related to Verilator☆38Updated 4 years ago
- Verilog Fundamentals Explained for Beginners and Professionals☆19Updated 2 years ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆49Updated last year
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆32Updated 4 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆64Updated 3 years ago