JeffDeCola / my-verilog-examples
A place to keep my synthesizable verilog examples.
☆30Updated last year
Related projects ⓘ
Alternatives and complementary repositories for my-verilog-examples
- Xilinx AXI VIP example of use☆32Updated 3 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆59Updated 3 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆43Updated 2 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆23Updated 5 months ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆28Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆58Updated last month
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- Implementation of post-process coverage, and batch waveform search☆15Updated 3 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆22Updated 3 years ago
- Open source ISS and logic RISC-V 32 bit project☆40Updated this week
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆53Updated 2 weeks ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆24Updated 3 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆22Updated last month
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆29Updated 5 months ago
- Implementing Different Adder Structures in Verilog☆60Updated 5 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆37Updated 3 years ago
- General Purpose AXI Direct Memory Access☆44Updated 6 months ago
- ☆37Updated 5 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆16Updated 11 months ago
- Contains commonly used UVM components (agents, environments and tests).☆26Updated 6 years ago
- This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit☆18Updated 6 years ago
- ☆22Updated 8 months ago
- HLS for Networks-on-Chip☆31Updated 3 years ago
- SRAM☆20Updated 4 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆43Updated 3 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆58Updated 2 months ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆48Updated 10 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆64Updated 2 months ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆21Updated 6 years ago