x653 / xv6-riscv-fpga
Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).
☆46Updated 2 years ago
Alternatives and similar repositories for xv6-riscv-fpga:
Users that are interested in xv6-riscv-fpga are comparing it to the libraries listed below
- FPGA based microcomputer sandbox for software and RTL experimentation☆54Updated this week
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆54Updated last year
- Another tiny RISC-V implementation☆54Updated 3 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆80Updated this week
- Reusable Verilog 2005 components for FPGA designs☆41Updated last month
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 2 years ago
- 3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.☆78Updated 4 years ago
- Dual-issue RV64IM processor for fun & learning☆60Updated last year
- Example Verilog code for Ulx3s☆40Updated 2 years ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆45Updated last year
- 64-bit multicore Linux-capable RISC-V processor☆89Updated 7 months ago
- Verilog implementation of a RISC-V core☆114Updated 6 years ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆96Updated 3 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated 11 months ago
- NucleusRV - A 32-bit 5 staged pipelined risc-v core.☆66Updated this week
- Minimal DVI / HDMI Framebuffer☆79Updated 4 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆89Updated 4 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆150Updated this week
- RISC-V implementation of RV32I for FPGA board Tang Nano 9K utilizing on-board burst PSRAM, flash and SD card☆28Updated this week
- Linux capable RISC-V SoC designed to be readable and useful.☆142Updated 6 months ago
- Port of MIT's xv6 OS to 32 bit RISC V☆35Updated 2 years ago
- This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…☆81Updated 4 years ago
- A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board☆29Updated 3 years ago
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆71Updated last year
- A simple 8 bit UART implementation in Verilog, with tests and timing diagrams☆29Updated last year
- ☆34Updated 5 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆92Updated last month
- SoftCPU/SoC engine-V☆54Updated 3 weeks ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆45Updated 5 months ago