Alternatives and similar repositories for pershing

Users that are interested in pershing are comparing it to the libraries listed below

• qmn / dewey
  C version of PERSHING, a place-and-route tool for Minecraft Redstone circuits
  ☆23Updated 7 years ago
• marlls1989 / arv
  ARV: Asynchronous RISC-V Go High-level Functional Model
  ☆25Updated 4 years ago
• seunghyukcho / pipelined-cpu-verilog
  Verilog implementation of pipelined cpu
  ☆12Updated 4 years ago
• Kenny2github / V2MC
  Synthesize Verilog to Minecraft redstone
  ☆21Updated last year
• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆86Updated 2 years ago
• XekriRedmane / riscv-reboot
  ☆43Updated 4 years ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆125Updated 9 years ago
• rubund / graywolf
  ☆114Updated 5 years ago
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆99Updated 3 years ago
• hgeisse / eco32
  32-Bit RISC microprocessor system for FPGA boards
  ☆36Updated last year
• geky / gb
  The Original Nintendo Gameboy in Verilog
  ☆61Updated 11 years ago
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆56Updated 7 years ago
• Ravenslofty / 74xx-liberty
  ☆70Updated 2 years ago
• whitequark / bfcpu2
  A pipelined brainfuck softcore in Verilog
  ☆19Updated 11 years ago
• nickmqb / fpga_craft
  A voxel game/Minecraft clone for the iCE40 UP5K FPGA
  ☆208Updated 3 months ago
• haojunliu / OpenFPGA
  OpenFPGA
  ☆34Updated 7 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 10 months ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆34Updated 9 years ago
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆60Updated 6 years ago
• pepijndevos / seqpu
  A bit-serial CPU
  ☆19Updated 6 years ago
• jrmoserbaltimore / risc-v-cpu-asynchronous
  A RISC-V CPU implementation
  ☆17Updated 5 years ago
• featherweight-ip / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 4 years ago
• zhemao / ez8
  The Easy 8-bit Processor
  ☆187Updated 11 years ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆45Updated 3 years ago
• jamieiles / oldland-cpu
  Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools
  ☆126Updated 9 years ago
• tvanas / r-vex
  A reconfigurable and extensible VLIW processor implemented in VHDL
  ☆39Updated 10 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆186Updated last year
• SymbiFlow / vtr-verilog-to-routing
  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆38Updated last year
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆89Updated last year
• laforest / Octavo
  Verilog FPGA Parts Library. Old Octavo soft-CPU project.
  ☆76Updated 6 years ago