Alternatives and similar repositories for System-on-Chip-Design-with-Arm-Cortex-M-Processors

Users that are interested in System-on-Chip-Design-with-Arm-Cortex-M-Processors are comparing it to the libraries listed below

• mikeroyal / Verilog-SystemVerilog-Guide
  Verilog/SystemVerilog Guide
  ☆78Updated 2 years ago
• kmkalpana2001 / DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING
  ☆47Updated last year
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆85Updated 2 months ago
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆188Updated last month
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆76Updated 6 years ago
• arm-university / Advanced-System-on-Chip-Design-Education-Kit
  Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…
  ☆119Updated 3 months ago
• black-parrot-hdk / zynq-parrot
  BlackParrot on Zynq
  ☆47Updated 3 weeks ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆60Updated last month
• arm-university / Introduction-to-SoC-Design-Education-Kit
  Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…
  ☆151Updated 3 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 6 months ago
• Fraunhofer-IMS / airisc_core_complex
  Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
  ☆99Updated 6 months ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆68Updated 5 years ago
• wyvernSemi / pcievhost
  PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities
  ☆129Updated 3 weeks ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆132Updated 3 months ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆81Updated 3 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆76Updated 5 years ago
• learn-cocotb / tutorial
  Complete tutorial code.
  ☆22Updated last year
• arm-university / SoC-design-and-prototyping-Research-Enablement-Kit
  SoC design & prototyping
  ☆16Updated 7 months ago
• Learning-Chips-Lab / OpenEye
  The Open Source Hardware Accelerator for Efficient Neural Network Inference
  ☆48Updated last week
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆69Updated 3 months ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆78Updated 3 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆61Updated 3 years ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆48Updated 3 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆62Updated last year
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆145Updated last week
• sheldonucr / ee260_lab
  EE 260 Winter 2017: Advanced VLSI Design
  ☆68Updated 9 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆68Updated 11 months ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆118Updated 2 years ago
• mitya1337 / Simple_I2C
  Simple implementation of I2C interface written on Verilog and SystemC
  ☆47Updated 8 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆43Updated 4 years ago