Alternatives and similar repositories for System-on-Chip-Design-with-Arm-Cortex-M-Processors:

Users that are interested in System-on-Chip-Design-with-Arm-Cortex-M-Processors are comparing it to the libraries listed below

• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆26Updated 6 months ago
• arm-university / SoC-design-and-prototyping-Research-Enablement-Kit
  SoC design & prototyping
  ☆12Updated 3 years ago
• arm-university / Modern-System-on-Chip-Design-on-Arm
  A textbook on system on chip design using Arm Cortex-A
  ☆26Updated 10 months ago
• snbk001 / 100DaysofRTL
  100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…
  ☆34Updated 2 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆57Updated 4 years ago
• mikeroyal / Verilog-SystemVerilog-Guide
  Verilog/SystemVerilog Guide
  ☆61Updated last year
• black-parrot-hdk / zynq-parrot
  BlackParrot on Zynq
  ☆37Updated 3 weeks ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆64Updated last month
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆30Updated 5 months ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆38Updated 10 months ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆48Updated 10 months ago
• learn-cocotb / tutorial
  Complete tutorial code.
  ☆17Updated 11 months ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆56Updated last year
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆64Updated 5 years ago
• merledu / azadi-soc
  Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.
  ☆29Updated last year
• kmkalpana2001 / DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING
  ☆28Updated 11 months ago
• The-OpenROAD-Project / megaboom
  ☆25Updated 2 weeks ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆26Updated 4 years ago
• arm-university / Advanced-System-on-Chip-Design-Education-Kit
  Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…
  ☆96Updated 8 months ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆44Updated 3 years ago
• SingularityKChen / SystemC-Training
  SystemC training aimed at TLM.
  ☆27Updated 4 years ago
• merledu / TileLink
  TileLink Uncached Lightweight (TL-UL) implementation on Chisel.
  ☆20Updated 4 years ago
• AsFigo / apb_uvc_verilator
  APB UVC ported to Verilator
  ☆11Updated last year
• aasthadave9 / Advanced-Physical-Design-Using-OpenLANE-Sky130
  This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…
  ☆15Updated 3 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆34Updated 3 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆53Updated 2 weeks ago
• EngAhmed21 / RISC-V-Processor-with-Pipelining
  Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…
  ☆14Updated last year
• kerimturak / tcore-rv32imc
  ☆12Updated last month
• embedded-explorer / Open-Source-RTL-Design
  This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop
  ☆35Updated 3 years ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆28Updated last week