arm-university / SoC-design-and-prototyping-Research-Enablement-KitLinks
SoC design & prototyping
☆13Updated last week
Alternatives and similar repositories for SoC-design-and-prototyping-Research-Enablement-Kit
Users that are interested in SoC-design-and-prototyping-Research-Enablement-Kit are comparing it to the libraries listed below
Sorting:
- A textbook on system on chip design using Arm Cortex-A☆32Updated 2 weeks ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- Development of a Network on Chip Simulation using SystemC.☆33Updated 7 years ago
- SystemC training aimed at TLM.☆30Updated 4 years ago
- A reference book on System-on-Chip Design☆29Updated last week
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated last week
- ☆27Updated 5 years ago
- BlackParrot on Zynq☆42Updated 3 months ago
- Xilinx AXI VIP example of use☆40Updated 4 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆28Updated 3 weeks ago
- General Purpose AXI Direct Memory Access☆51Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆51Updated 4 years ago
- Complete tutorial code.☆21Updated last year
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆27Updated 3 years ago
- ☆34Updated 6 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 4 months ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆23Updated 6 years ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆16Updated last year
- ☆30Updated 2 months ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- System Verilog BootCamp☆24Updated 3 years ago
- Advanced Architecture Labs with CVA6☆62Updated last year
- ☆14Updated 2 years ago
- DUTH RISC-V Microprocessor☆20Updated 6 months ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆21Updated 4 years ago
- ☆12Updated 2 months ago
- Neural Network accelerator powered by MVUs and RISC-V.☆13Updated 11 months ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆19Updated 10 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago