arm-university / SoC-design-and-prototyping-Research-Enablement-KitLinks
SoC design & prototyping
☆16Updated 5 months ago
Alternatives and similar repositories for SoC-design-and-prototyping-Research-Enablement-Kit
Users that are interested in SoC-design-and-prototyping-Research-Enablement-Kit are comparing it to the libraries listed below
Sorting:
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆71Updated 4 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- BlackParrot on Zynq☆47Updated this week
- North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog☆11Updated 8 years ago
- Development of a Network on Chip Simulation using SystemC.☆33Updated 8 years ago
- A repository for SystemC Learning examples☆72Updated 3 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- ☆37Updated 6 years ago
- ☆19Updated last month
- Contains commonly used UVM components (agents, environments and tests).☆31Updated 7 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆54Updated 4 years ago
- CORE-V MCU UVM Environment and Test Bench☆24Updated last year
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆16Updated last year
- SystemC training aimed at TLM.☆34Updated 5 years ago
- ☆30Updated 3 weeks ago
- ☆78Updated 11 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 9 months ago
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆31Updated 2 months ago
- HLS for Networks-on-Chip☆37Updated 4 years ago
- The purpose of the repo is to support CORE-V Wally architectural verification☆15Updated last week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆93Updated 2 weeks ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last week
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- ☆27Updated 6 years ago
- ☆67Updated 4 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated last week
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆124Updated last week
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆17Updated last month
- SystemVerilog Functional Coverage for RISC-V ISA☆32Updated 5 months ago