Alternatives and similar repositories for serv_soc

Users that are interested in serv_soc are comparing it to the libraries listed below

• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 10 months ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆92Updated 6 years ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆93Updated 7 years ago
• featherweight-ip / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 4 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆70Updated last month
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 7 years ago
• mattvenn / vga-clock
  Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
  ☆62Updated 4 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆71Updated 3 years ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆125Updated 9 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆97Updated 5 years ago
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆39Updated 4 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆66Updated 3 weeks ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆51Updated 3 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆110Updated this week
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆83Updated 5 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆44Updated last month
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆131Updated 2 years ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆51Updated 10 months ago
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆33Updated 5 years ago
• cloudxcc / Arduissimo
  Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).
  ☆22Updated 6 years ago
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆47Updated last year
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆63Updated 7 years ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆59Updated 2 months ago
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆72Updated 7 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated 2 years ago
• olofk / vidbo
  Virtual Development Board
  ☆64Updated 4 years ago
• olofk / observer
  ☆43Updated 5 years ago
• projf / fpgatools
  Tools for FPGA development.
  ☆49Updated 6 months ago
• no2fpga / no2usb
  Nitro USB FPGA core
  ☆86Updated last year