DaveBerkeley / serv_socLinks
SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.
☆31Updated 5 years ago
Alternatives and similar repositories for serv_soc
Users that are interested in serv_soc are comparing it to the libraries listed below
Sorting:
- Featherweight RISC-V implementation☆53Updated 3 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆69Updated 3 weeks ago
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- SoftCPU/SoC engine-V☆55Updated 9 months ago
- Bitstream relocation and manipulation tool.☆50Updated 3 years ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 4 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆125Updated 9 years ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated 2 months ago
- Wishbone interconnect utilities☆44Updated 3 weeks ago
- Basic USB 1.1 Host Controller for small FPGAs☆97Updated 5 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆109Updated 3 weeks ago
- PicoRV☆43Updated 5 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- ☆63Updated 7 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆82Updated 5 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆71Updated 3 years ago
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆22Updated 6 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆93Updated 7 years ago
- Generic Logic Interfacing Project☆48Updated 5 years ago
- Virtual Development Board☆64Updated 4 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆58Updated last month
- OpenFPGA☆34Updated 7 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆47Updated last year
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- Projects published on controlpaths.com and hackster.io☆42Updated 3 years ago
- Reusable Verilog 2005 components for FPGA designs☆49Updated 3 weeks ago
- Extensible FPGA control platform☆61Updated 2 years ago
- Spen's Official OpenOCD Mirror☆51Updated 9 months ago
- A collection of debugging busses developed and presented at zipcpu.com☆42Updated last year
- A configurable USB 2.0 device core☆32Updated 5 years ago