SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.
☆31Sep 10, 2020Updated 5 years ago
Alternatives and similar repositories for serv_soc
Users that are interested in serv_soc are comparing it to the libraries listed below
Sorting:
- Verilog FPGA code : including experimental DSP audio processor☆13Dec 1, 2020Updated 5 years ago
- A SoC for DOOM☆20Apr 11, 2021Updated 4 years ago
- MAC system with IEEE754 compatibility☆13Nov 22, 2023Updated 2 years ago
- powerpc processor prototype and an example of semiconductor startup biz plan☆14Feb 2, 2019Updated 7 years ago
- Compiler for micro C written in erlang.☆17Feb 20, 2013Updated 13 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆11Dec 14, 2022Updated 3 years ago
- Simulations and designs for bit serial ALU implemented in TTL circuitry. Also bit serial cpu architectures - all simulated using H. Neem…☆12Aug 26, 2022Updated 3 years ago
- ZC RISCV CORE☆12Dec 19, 2019Updated 6 years ago
- ☆11Jun 29, 2021Updated 4 years ago
- AGRV2K裸奔测试工程☆29Jan 5, 2024Updated 2 years ago
- ☆10Nov 2, 2023Updated 2 years ago
- General Purpose Graphics Processing Unit (GPGPU) IP Core☆11Jul 4, 2014Updated 11 years ago
- Nitro USB FPGA core☆86Updated this week
- ice40 USB Analyzer☆57Aug 8, 2020Updated 5 years ago
- A tiny FP8 multiplication unit written in Verilog. TinyTapeout 2 submission.☆14Nov 23, 2022Updated 3 years ago
- GDB Stub for RT-Thread(already in RT-Thread master)☆17Jan 10, 2015Updated 11 years ago
- RISC-V vector extension ISA simulation☆16Jun 11, 2019Updated 6 years ago
- Very simple MicroPython module to use a generic 64Mbit PSRAM (ie Adafruit 4677) with a Raspberry Pi Pico (RP2040)☆14Jun 10, 2021Updated 4 years ago
- Cheapest UAC2 using STM32F407+USB3300☆21Feb 26, 2025Updated last year
- ☆14Nov 5, 2017Updated 8 years ago
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆21Feb 4, 2025Updated last year
- Erlang Performance Measurements☆34May 28, 2022Updated 3 years ago
- Embedded Erlang project☆18Mar 1, 2011Updated 15 years ago
- ☆18May 24, 2021Updated 4 years ago
- Utilities for the ECP5 FPGA☆17Aug 5, 2021Updated 4 years ago
- generic web server behaviour for conveniently building REST based interfaces☆34Aug 22, 2010Updated 15 years ago
- High performance narrow-band receiver. Most of the important parts are fabbed in the US. The superH is a 480MHz STM32H743 based SDR cap…☆18Jul 26, 2022Updated 3 years ago
- SAR ADC on tiny tapeout☆47Jan 29, 2025Updated last year
- Open-source high performance AXI4-based HyperRAM memory controller☆83Oct 6, 2022Updated 3 years ago
- SPI-Flash XIP Interface (Verilog)☆48Oct 24, 2021Updated 4 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 3 years ago
- PCIe adapter for an FPGA accelerator for Open CloudServer☆25May 31, 2020Updated 5 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆21Dec 10, 2018Updated 7 years ago
- AGM bitstream utilities and decoded files from Supra☆48Aug 9, 2025Updated 6 months ago
- An Erlang INI parser☆28Jan 2, 2013Updated 13 years ago
- Simple, Fast, Permanent Erlang Worker Pool☆40Oct 3, 2015Updated 10 years ago
- SDR prototype with 90 MHz bandwidth, built as a demonstrator for hsdaoh☆29Jun 2, 2024Updated last year
- Erlang bindings to llvm-c☆23Mar 13, 2012Updated 13 years ago
- SpinalHDL USB system for the ULPI based Arrow DECA board☆20Jan 9, 2022Updated 4 years ago