kole-huang / picorv32_socLinks
picorv32_soc, simulation env, FPGA, boot code, RTOS
☆15Updated 7 years ago
Alternatives and similar repositories for picorv32_soc
Users that are interested in picorv32_soc are comparing it to the libraries listed below
Sorting:
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆130Updated 5 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆127Updated 6 years ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆75Updated last year
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆67Updated 5 months ago
- ☆96Updated 2 months ago
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- ☆69Updated 3 months ago
- TCP/IP controlled VPI JTAG Interface.☆67Updated 9 months ago
- Ethernet 10GE MAC☆46Updated 11 years ago
- ☆26Updated 3 years ago
- ☆79Updated 3 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆79Updated 3 years ago
- Ethernet switch implementation written in Verilog☆54Updated 2 years ago
- 国产VU13P加速卡资料☆79Updated 7 months ago
- Simple implementation of I2C interface written on Verilog and SystemC☆44Updated 8 years ago
- ☆87Updated 8 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 10 years ago
- Verilog Ethernet Switch (layer 2)☆49Updated 2 years ago
- A python project to automatically generate the UVM testbench document.☆21Updated last year
- native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches☆46Updated 10 years ago
- JTAG Test Access Port (TAP)☆36Updated 11 years ago
- Small (Q)SPI flash memory programmer in Verilog☆65Updated 3 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆91Updated 3 years ago
- Verilog UART☆185Updated 12 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆157Updated 8 months ago
- ☆119Updated 3 weeks ago
- AXI Interface Nand Flash Controller (Sync mode)☆97Updated last year
- UART -> AXI Bridge☆63Updated 4 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆41Updated 5 years ago
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆76Updated 4 years ago