Alternatives and similar repositories for ISA_Formal_Spec_Public_Review:

Users that are interested in ISA_Formal_Spec_Public_Review are comparing it to the libraries listed below

• rsnikhil / Forvis_RISCV-ISA-Spec
  Formal specification of RISC-V Instruction Set
  ☆100Updated 4 years ago
• mit-plv / riscv-semantics
  A formal semantics of the RISC-V ISA in Haskell
  ☆163Updated last year
• GaloisInc / grift
  Galois RISC-V ISA Formal Tools
  ☆56Updated last year
• SRI-CSL / l3riscv
  An executable specification of the RISCV ISA in L3.
  ☆41Updated 6 years ago
• mit-plv / kami
  A Platform for High-Level Parametric Hardware Specification and its Modular Verification
  ☆151Updated 6 months ago
• mit-plv / riscv-coq
  RISC-V Specification in Coq
  ☆111Updated 2 months ago
• project-oak / silveroak
  Formal specification and verification of hardware, especially for security and privacy.
  ☆124Updated 2 years ago
• rsnikhil / RISCV_ISA_Formal_Spec_in_BSV
  A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
  ☆20Updated 7 years ago
• cliffordwolf / xbitmanip
  RISC-V XBitmanip Extension
  ☆27Updated 6 years ago
• CTSRD-CHERI / bluecheck
  A generic test bench written in Bluespec
  ☆51Updated 4 years ago
• rems-project / sail-arm
  Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model
  ☆77Updated last month
• mit-plv / koika
  A core language for rule-based hardware design 🦑
  ☆147Updated 5 months ago
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆99Updated 5 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆141Updated last month
• POETSII / tinsel
  Manythread RISC-V overlay for FPGA clusters
  ☆36Updated 2 years ago
• CakeML / hardware
  Verilog development and verification project for HOL4
  ☆25Updated 4 months ago
• BSVLang / Main
  Main page
  ☆125Updated 5 years ago
• freechipsproject / firrtl-interpreter
  A scala based simulator for circuits described by a LoFirrtl file
  ☆47Updated 2 years ago
• blarney-lang / blarney
  Haskell library for hardware description
  ☆102Updated 4 months ago
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆50Updated 8 years ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 5 years ago
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆58Updated last week
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆209Updated last year
• TeamVoss / VossII
  The source code to the Voss II Hardware Verification Suite
  ☆57Updated last week
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆322Updated 3 years ago
• adamwalker / clash-riscv
  A RiscV processor implementing the RV32I instruction set written in Clash
  ☆53Updated 6 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆36Updated 3 years ago
• riscvarchive / riscv-fesvr
  RISC-V Frontend Server
  ☆62Updated 5 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆155Updated 4 years ago
• pretis / flexpret
  A time-predictable processor for mixed-criticality systems
  ☆58Updated 4 months ago