Alternatives and similar repositories for r2vm

Users that are interested in r2vm are comparing it to the libraries listed below

• riscv / riscv-cfi
  This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …
  ☆87Updated this week
• KuangjuX / hypocaust
  hypocaust, a S-mode trap and emulate type-1 hypervisor run on RISC-V machine.
  ☆48Updated 2 years ago
• riscv / riscv-smmtt
  This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…
  ☆52Updated this week
• diodesign / diosix
  A lightweight, secure, multiprocessor bare-metal hypervisor written in Rust for RISC-V
  ☆196Updated 5 months ago
• shady831213 / terminus
  A riscv isa simulator in rust.
  ☆65Updated last year
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆151Updated 2 weeks ago
• riscv-software-src / riscof
  ☆83Updated 2 months ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆119Updated last week
• rivosinc / salus
  Risc-V hypervisor for TEE development
  ☆117Updated last week
• riscv / virtual-memory
  ☆36Updated 3 years ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆153Updated 3 years ago
• TianhuaTao / uCore-SMP
  A Symmetric Multiprocessing OS Kernel over RISC-V
  ☆31Updated 3 years ago
• riscv-non-isa / riscv-security-model
  RISC-V Security Model
  ☆30Updated this week
• riscv-non-isa / riscv-c-api-doc
  Documentation of the RISC-V C API
  ☆76Updated this week
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆59Updated last week
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆79Updated 3 weeks ago
• fintelia / riscv-decode
  Simple library for decoding RISC-V instructions
  ☆24Updated 10 months ago
• rcore-os / trapframe-rs
  Handle TrapFrame across kernel and user space on multiple ISAs.
  ☆33Updated 11 months ago
• riscv / riscv-plic-spec
  PLIC Specification
  ☆140Updated 2 years ago
• KuangjuX / hypocaust-2
  hypocaust-2, a type-1 hypervisor with H extension run on RISC-V machine
  ☆55Updated last year
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆95Updated 2 months ago
• rustsbi / rustsbi-hifive-unmatched
  RustSBI support on SiFive FU740 board; FU740 is a five-core heterogeneous processor with four SiFive U74 cores, and one SiFive S7 core
  ☆17Updated last year
• ria-jit / ria-jit
  Lightweight and performant dynamic binary translation for RISC–V code on x86–64
  ☆61Updated 4 years ago
• riscv / riscv-cheri
  This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…
  ☆72Updated this week
• Amanieu / a-tale-of-binary-translation
  Simple RISC-V emulator presented at Rust Nation 2023
  ☆64Updated 2 years ago
• riscv / riscv-j-extension
  Working Draft of the RISC-V J Extension Specification
  ☆187Updated last month
• open-s4c / vsyncer
  Verification and optimization tool for concurrent code
  ☆25Updated 2 months ago
• riscv / riscv-spmp
  The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by…
  ☆16Updated last month
• kvm-riscv / howto
  KVM RISC-V HowTOs
  ☆47Updated 3 years ago
• ucb-bar / libgloss-htif
  A libgloss replacement for RISC-V that supports HTIF
  ☆38Updated last year