CTSRD-CHERI / llvm-project
Fork of LLVM adding CHERI support
☆52Updated 2 weeks ago
Alternatives and similar repositories for llvm-project
Users that are interested in llvm-project are comparing it to the libraries listed below
Sorting:
- QEMU with support for CHERI☆58Updated 3 weeks ago
- Easily build and run CHERI related projects☆75Updated 2 weeks ago
- Example implementation of Arm's Architecture Specification Language (ASL)☆41Updated last week
- Example implementation of Arm's Architecture Specification Language (ASL)☆115Updated 5 years ago
- rmem public repo☆41Updated last month
- Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model☆79Updated last month
- Symbolic execution tool for Sail ISA specifications☆66Updated last month
- Some experiments with SMT solvers and GIMPLE IR☆74Updated this week
- CHERI-RISC-V model written in Sail☆59Updated last month
- Learning exercises for CHERI☆21Updated 6 months ago
- CHERI C/C++ Programming Guide☆31Updated 3 weeks ago
- CheriOS -- a minimal microkernel that demonstrates "clean-slate" CHERI memory protection and object capabilities☆40Updated 2 years ago
- A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one☆71Updated this week
- This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …☆87Updated this week
- Semantic model for aspects of ELF static linking and DWARF debug information☆44Updated 4 months ago
- UB-aware interpreter for LLVM debugging☆27Updated last week
- Tools to process ARM's Machine Readable Architecture Specification☆128Updated 5 years ago
- Verification of BPF JIT compilers☆55Updated last year
- llvm opt fuzzer and bounded exhaustive test generator☆39Updated 2 years ago
- Generates CIL MLIR dialect from C/C++ source.☆32Updated 4 years ago
- Delta assists you in minimizing "interesting" files subject to a test of their interestingness.☆29Updated 3 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆29Updated this week
- A (concrete or symbolic) implementation of IEEE-754 / SMT-LIB floating-point☆40Updated 2 months ago
- CHERI ISA Specification☆24Updated 10 months ago
- GNU Superoptimizer Version 2☆26Updated 3 years ago
- The website for freeCompilerCamp's classroom tutorials, using Github Pages.☆32Updated 3 years ago
- ☆88Updated 2 years ago
- Testing processors with Random Instruction Generation☆37Updated last month
- FreeBSD adapted for CHERI-RISC-V and Arm Morello.☆179Updated this week
- A formalization of the RVWMO (RISC-V) memory model☆32Updated 2 years ago