CTSRD-CHERI / llvm-project
Fork of LLVM adding CHERI support
☆51Updated this week
Alternatives and similar repositories for llvm-project:
Users that are interested in llvm-project are comparing it to the libraries listed below
- QEMU with support for CHERI☆58Updated this week
- Easily build and run CHERI related projects☆74Updated 3 weeks ago
- Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model☆77Updated 2 weeks ago
- Example implementation of Arm's Architecture Specification Language (ASL)☆115Updated 5 years ago
- rmem public repo☆41Updated 7 months ago
- CHERI C/C++ Programming Guide☆31Updated this week
- CHERI-RISC-V model written in Sail☆58Updated 3 weeks ago
- Example implementation of Arm's Architecture Specification Language (ASL)☆41Updated this week
- CheriOS -- a minimal microkernel that demonstrates "clean-slate" CHERI memory protection and object capabilities☆39Updated 2 years ago
- Some experiments with SMT solvers and GIMPLE IR☆73Updated last week
- Tools to process ARM's Machine Readable Architecture Specification☆126Updated 5 years ago
- Verification of BPF JIT compilers☆54Updated last year
- Lists of must-read papers (mainly security papers)☆28Updated 5 months ago
- A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one☆45Updated this week
- llvm opt fuzzer and bounded exhaustive test generator☆39Updated 2 years ago
- Generates CIL MLIR dialect from C/C++ source.☆32Updated 4 years ago
- CHERI ISA Specification☆24Updated 7 months ago
- Develop toolchain based on llvm to for Cpu0 processor☆45Updated last year
- Learning exercises for CHERI☆20Updated 4 months ago
- Delta assists you in minimizing "interesting" files subject to a test of their interestingness.☆28Updated 3 years ago
- CCG is a random C Code Generator☆43Updated 2 years ago
- Some experiments with SMT solvers and GIMPLE IR☆36Updated last year
- RISC-V Security Model☆30Updated this week
- Mirror of InriaForge SSABook repository: https://gforge.inria.fr/projects/ssabook/ (was scheduled for retirement at the end of 2020, was …☆138Updated 4 years ago
- RISC-V Instruction Set Metadata☆41Updated 6 years ago
- Symbolic execution tool for Sail ISA specifications☆66Updated last month
- A low-level intermediate representation for hardware description languages☆28Updated 4 years ago
- Testing processors with Random Instruction Generation☆33Updated 3 weeks ago
- A verification tool for many memory models☆83Updated this week
- Semantic model for aspects of ELF static linking and DWARF debug information☆43Updated 2 months ago