Alternatives and similar repositories for librpmi

Users that are interested in librpmi are comparing it to the libraries listed below

• zero-day-labs / riscv-iommu-demo
  RISC-V IOMMU Demo (Linux & Bao)
  ☆23Updated last year
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆46Updated 10 months ago
• riscv / riscv-aia
  ☆98Updated 3 months ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆42Updated last week
• riscv / riscv-smmtt
  This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…
  ☆64Updated last week
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆144Updated last week
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆107Updated 2 months ago
• bao-project / bao-demos
  A guide on how to build and use a set of Bao guest configurations for various platforms
  ☆47Updated last week
• riscvarchive / riscv-eabi-spec
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆27Updated 4 years ago
• riscv-non-isa / iopmp-spec
  This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protectio…
  ☆37Updated last week
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆71Updated last year
• josecm / rocket-chip
  Rocket Chip Generator
  ☆13Updated 4 years ago
• riscvarchive / riscv-CMOs
  ☆89Updated 3 months ago
• bao-project / bao-helloworld
  ☆12Updated 2 weeks ago
• five-embeddev / riscv-csr-access
  RISC-V CSR Access Routines
  ☆15Updated 2 years ago
• riscv-admin / iopmp
  Group administration repository for Tech: IOPMP Task Group
  ☆13Updated 11 months ago
• riscv / riscv-spmp
  The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by…
  ☆21Updated last week
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆37Updated last year
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆55Updated 11 months ago
• XUANTIE-RV / zero_stage_boot
  ☆15Updated 4 months ago
• riscvarchive / riscv-tee
  ☆38Updated 3 years ago
• luizinhosuraty / pciemu
  PCIe Device Emulation in QEMU
  ☆85Updated 2 years ago
• s094392 / riscv-bare-metal
  A RISC-V bare metal example
  ☆52Updated 3 years ago
• ARM-software / tarmac-trace-utilities
  Tools for analyzing and browsing Tarmac instruction traces.
  ☆79Updated last month
• riscv / riscv-plic-spec
  PLIC Specification
  ☆150Updated 3 months ago
• Xilinx / qemu-devicetrees
  Device trees used by QEMU to describe the hardware
  ☆54Updated 2 weeks ago
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆59Updated this week
• riscvarchive / security
  RISC-V Security HC admin repo
  ☆18Updated 10 months ago
• quic / qbox
  Qbox
  ☆70Updated 2 weeks ago
• riscv-non-isa / riscv-external-debug-security
  The RISC-V External Debug Security Specification
  ☆20Updated this week