DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM2 chips and DDR4 modules of different form factors. Six prototypes are available on different FPGA boards. Described in our preprint: https://arxiv.org/pdf/2211.05838.pdf
☆123Aug 10, 2025Updated 9 months ago
Alternatives and similar repositories for DRAM-Bender
Users that are interested in DRAM-Bender are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Source code & scripts for experimental characterization and demonstration of 1) simultaneous many-row activation, 2) up to nine-input maj…☆12May 17, 2024Updated 2 years ago
- SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. T…☆148Aug 24, 2023Updated 2 years ago
- ☆22Feb 26, 2023Updated 3 years ago
- ☆20Jun 20, 2020Updated 5 years ago
- Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and …☆557May 14, 2026Updated last week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- FPGA-driven memory tester for SO-DIMM DDR5 memory sticks☆33Dec 11, 2025Updated 5 months ago
- ☆14Oct 30, 2024Updated last year
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆76Dec 11, 2023Updated 2 years ago
- ☆15Apr 18, 2024Updated 2 years ago
- Processing in Memory Emulation☆27Feb 24, 2023Updated 3 years ago
- ☆151Jun 24, 2024Updated last year
- A Cycle-level simulator for M2NDP☆37Aug 14, 2025Updated 9 months ago
- The Artifact of NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering☆62Aug 11, 2024Updated last year
- A full-system, cycle-level simulator based on gem5 that provides complete support for all three CXL sub-protocols and all three types of …☆151May 11, 2026Updated 2 weeks ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Quick & Flexible Rack-Scale Computer Architecture Simulator☆53May 19, 2026Updated last week
- ☆99Mar 11, 2026Updated 2 months ago
- A survey of manufacturer-provided DRAM operating parameters and timings as specified by DRAM chip datasheets from between 1970 and 2021. …☆11May 4, 2022Updated 4 years ago
- ☆11Mar 3, 2025Updated last year
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆202Jan 8, 2026Updated 4 months ago
- TRRespass☆128May 5, 2021Updated 5 years ago
- PyGim is the first runtime framework to efficiently execute Graph Neural Networks (GNNs) on real Processing-in-Memory systems. It provide…☆36Apr 23, 2025Updated last year
- ☆14Jun 4, 2025Updated 11 months ago
- PIMeval simulator and PIMbench suite☆48Nov 22, 2025Updated 6 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- This is the respository that holds the artifacts of MICRO'23 -- Demystifying CXL Memory with True CXL-Ready Systems and CXL Memory Device…☆53Mar 17, 2024Updated 2 years ago
- DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator☆477Aug 3, 2024Updated last year
- This repository provides Pensieve, a security evaluation framework for microarchitectural defenses against speculative execution attacks.☆26Jan 17, 2024Updated 2 years ago
- Artifacts for "ZenHammer: Rowhammer Attacks on AMD Zen-based Platforms" (USENIX Security '24).☆61Jun 19, 2025Updated 11 months ago
- ☆78May 16, 2026Updated last week
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆76Dec 29, 2025Updated 4 months ago
- A RRAM addon for the NCSU FreePDK 45nm☆26Jan 10, 2022Updated 4 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆17Jan 30, 2023Updated 3 years ago
- RPCNIC: A High-Performance and Reconfigurable PCIe-attached RPC Accelerator [HPCA2025]☆15Dec 9, 2024Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Experimental breakout board for a signle 200-ball WFBGA LPDDR4 chip in SO-DIMM DDR4 form factor.☆22Dec 11, 2025Updated 5 months ago
- Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous pl…☆361Updated this week
- ☆81Apr 18, 2025Updated last year
- Trigger the rowhammer bug on ARMv8☆35Apr 14, 2019Updated 7 years ago
- A Rocket-Chip with a Dynamically Randomized LLC☆14Sep 18, 2024Updated last year
- NoC simulation using gem5 (a simple tul)☆14Mar 23, 2024Updated 2 years ago
- [PACT'24] GraNNDis. A fast and unified distributed graph neural network (GNN) training framework for both full-batch (full-graph) and min…☆10Aug 13, 2024Updated last year