CMU-SAFARI / DRAM-Bender
DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM2 chips and DDR4 modules of different form factors. Six prototypes are available on different FPGA boards. Described in our preprint: https://arxiv.org/pdf/2211.05838.pdf
☆65Updated 6 months ago
Alternatives and similar repositories for DRAM-Bender:
Users that are interested in DRAM-Bender are comparing it to the libraries listed below
- SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. T…☆130Updated last year
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆62Updated 8 months ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆62Updated last year
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- The official repository for the gem5 resources sources.☆65Updated last month
- Heterogeneous simulator for DECADES Project☆32Updated 10 months ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 6 years ago
- ☆32Updated 4 years ago
- Source code for the cycle-level simulator and RTL implementation of BlockHammer proposed in our HPCA 2021 paper: Yaglikci et. al., "Block…☆18Updated 2 years ago
- ☆91Updated last year
- gem5 Tips & Tricks☆67Updated 5 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆61Updated 2 years ago
- The OpenPiton Platform☆28Updated last year
- The gem5 Bootcamp 2022 environment. Archived.☆36Updated 8 months ago
- ☆78Updated last year
- Quick & Flexible Rack-Scale Computer Architecture Simulator☆35Updated 2 weeks ago
- Artifact, reproducibility, and testing utilites for gem5☆21Updated 3 years ago
- A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…☆72Updated 6 months ago
- Fast and accurate DRAM power and energy estimation tool☆151Updated this week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- ☆24Updated last year
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆23Updated 2 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 2 years ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆88Updated 11 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆64Updated last week
- Tests for example Rocket Custom Coprocessors☆73Updated 5 years ago
- Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)☆61Updated 5 years ago
- ☆13Updated 2 years ago