Alternatives and similar repositories for gem5-RISC-V-FS-Linux

Users that are interested in gem5-RISC-V-FS-Linux are comparing it to the libraries listed below

• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆101Updated 6 years ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆69Updated 2 weeks ago
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆117Updated 7 months ago
• sparcians / map
  Modeling Architectural Platform
  ☆194Updated this week
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆180Updated last week
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆135Updated 2 years ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆96Updated this week
• riscv / riscv-CMOs
  ☆86Updated 3 years ago
• riscv-ovpsim / imperas-riscv-tests
  ☆181Updated last year
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆69Updated 11 months ago
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆62Updated 2 years ago
• OpenXiangShan / GEM5
  ☆89Updated this week
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆88Updated 2 months ago
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆42Updated 5 months ago
• ramisheikh / cbp2025
  Championship Branch Prediction 2025
  ☆49Updated last month
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆109Updated 2 years ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆81Updated last month
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆52Updated 5 years ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆68Updated 8 months ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆123Updated this week
• VerticalResearchGroup / microbench
  Extremely Simple Microbenchmarks
  ☆34Updated 7 years ago
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆171Updated 7 months ago
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆179Updated 6 years ago
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆54Updated last week
• riscv-boom / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆40Updated 6 years ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆154Updated 3 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆65Updated last year
• machineware-gmbh / vcml
  A modeling library with virtual components for SystemC and TLM simulators
  ☆160Updated this week
• Xilinx / systemctlm-cosim-demo
  QEMU libsystemctlm-soc co-simulation demos.
  ☆149Updated last month
• riscv-boom / boom-attacks
  Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)
  ☆64Updated 5 years ago