Alternatives and similar repositories for gem5-RISC-V-FS-Linux:

Users that are interested in gem5-RISC-V-FS-Linux are comparing it to the libraries listed below

• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆98Updated 6 years ago
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆108Updated last month
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆61Updated 6 months ago
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆34Updated 4 months ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆83Updated 2 weeks ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆101Updated 3 weeks ago
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆16Updated last week
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆64Updated 5 months ago
• OpenXiangShan / GEM5
  ☆72Updated this week
• riscv / riscv-CMOs
  ☆82Updated 2 years ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆73Updated last year
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆70Updated 3 weeks ago
• arm-university / arm-gem5-rsk
  Official repository of the Arm Research Starter Kit on System Modeling using gem5
  ☆113Updated last year
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆58Updated last year
• gem5bootcamp / gem5-bootcamp-env
  The gem5 Bootcamp 2022 environment. Archived.
  ☆36Updated 6 months ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆128Updated 2 years ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆49Updated 4 years ago
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆123Updated last week
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆148Updated this week
• VerticalResearchGroup / microbench
  Extremely Simple Microbenchmarks
  ☆30Updated 6 years ago
• esl-epfl / gem5-X
  The gem5-X open source framework (based on the gem5 simulator)
  ☆38Updated last year
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆54Updated last year
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆45Updated 2 weeks ago
• riscv-ovpsim / imperas-riscv-tests
  ☆166Updated last year
• riscv-stc / riscv-matrix-spec
  RISC-V Matrix Specification
  ☆16Updated last month
• TeCSAR-UNCC / gem5-SALAM
  ☆88Updated 11 months ago
• riscv / riscv-aclint
  ☆42Updated 3 years ago
• sifive / block-inclusivecache-sifive
  ☆77Updated 2 years ago
• eric-rotenberg / CVP
  Championship Value Prediction (CVP) simulator.
  ☆15Updated 3 years ago
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆31Updated last year