Alternatives and similar repositories for gem5-RISC-V-FS-Linux

Users that are interested in gem5-RISC-V-FS-Linux are comparing it to the libraries listed below

• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆66Updated 11 months ago
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆116Updated 6 months ago
• OpenXiangShan / GEM5
  ☆86Updated this week
• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆99Updated 6 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆68Updated 10 months ago
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆61Updated 2 years ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆85Updated 3 weeks ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆134Updated 2 years ago
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆41Updated 4 months ago
• riscv-stc / riscv-matrix-spec
  RISC-V Matrix Specification
  ☆22Updated 6 months ago
• riscv / riscv-CMOs
  ☆86Updated 3 years ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆74Updated 5 years ago
• hushenwei2000 / rvv-atg
  RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…
  ☆15Updated last year
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆18Updated last week
• riscv-boom / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆40Updated 6 years ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆94Updated 2 months ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆109Updated 2 years ago
• cry-daniel / Computer-Architecture-Learning
  ☆61Updated 2 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆78Updated last week
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆31Updated 2 years ago
• riscv-stc / riscv-matrix-project
  Top project for RISC-V Matrix extension proposal and related opensource implementations.
  ☆30Updated last year
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆52Updated 5 years ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆77Updated this week
• ucb-bar / riscv-benchmarks
  ☆27Updated 8 years ago
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆42Updated 3 years ago
• VerticalResearchGroup / microbench
  Extremely Simple Microbenchmarks
  ☆33Updated 7 years ago
• sparcians / map
  Modeling Architectural Platform
  ☆190Updated this week
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆98Updated 3 weeks ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆195Updated 10 months ago