nandland / memoryLinks
Single Port RAM, Dual Port RAM, FIFO
☆24Updated 3 years ago
Alternatives and similar repositories for memory
Users that are interested in memory are comparing it to the libraries listed below
Sorting:
- JESD204b modules in VHDL☆30Updated 6 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆59Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆33Updated 4 months ago
- Ethernet MAC 10/100 Mbps☆83Updated 5 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆48Updated last year
- UART models for cocotb☆29Updated 2 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆36Updated 4 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆36Updated last year
- 1G eth UDP / IP Stack☆9Updated 10 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated 3 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 10 years ago
- Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA☆32Updated 4 years ago
- I2C controller core☆46Updated 2 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆55Updated 4 years ago
- Various utilities for working with FPGAs☆13Updated 9 years ago
- I2C models for cocotb☆35Updated 3 months ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- Generic FIFO implementation with optional FWFT☆58Updated 5 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- Hamming ECC Encoder and Decoder to protect memories☆33Updated 4 months ago
- Small (Q)SPI flash memory programmer in Verilog☆63Updated 2 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- Wishbone interconnect utilities☆41Updated 4 months ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆45Updated 9 years ago
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆24Updated 2 years ago
- This repository in a walk through the entire process of PLL IC designing from the tools to the final tapeout.☆20Updated 3 years ago
- SDRAM controller for MIPSfpga+ system☆23Updated 4 years ago