aionnetwork / aion_epic_fpgaminerLinks
FPGA referrence implementation for aion equihash 2109
☆14Updated 6 years ago
Alternatives and similar repositories for aion_epic_fpgaminer
Users that are interested in aion_epic_fpgaminer are comparing it to the libraries listed below
Sorting:
- SHA256 in (System-) Verilog / Open Source FPGA Miner☆79Updated 7 years ago
- Mining CryptoNight Haven on the Varium C1100☆10Updated 3 years ago
- An open source FPGA miner for Blakecoin☆52Updated 10 years ago
- Open source hardware implementation of classic CryptoNight☆38Updated 2 years ago
- An Open Source FPGA GroestlCoin Miner☆10Updated 7 years ago
- Cryptonight Monero Verilog code for ASIC☆20Updated 7 years ago
- Example verilog / miner for crypto mining using AWS F1 instances☆30Updated 7 years ago
- A litecoin scrypt miner implemented with FPGA on-chip memory.☆288Updated 10 years ago
- A completely open source implementation of a Bitcoin Miner for Altera FPGAs. This project hopes to promote the free and open development …☆51Updated 12 years ago
- Cryptography accelerator ASIC (for AES128/AES256 and SHA256) using Skywater 130nm process node (main project repo). Taped out in December…☆22Updated 4 years ago
- Zcash FPGA acceleration engine☆125Updated 4 years ago
- DE10 NANO SHA3-256 Proof of Work Miner☆13Updated 4 years ago
- ☆12Updated 2 years ago
- A simplified version of an FPGA bitcoin miner☆53Updated 6 years ago
- A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open d…☆173Updated 3 years ago
- VHDL FPGA design of an optimized Blake2b pipeline to mine Siacoin☆62Updated 7 years ago
- SQRL Port of ethminer☆11Updated 4 years ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆38Updated last year
- Bitcoin miner for Xilinx FPGAs☆97Updated 12 years ago
- Hardware implementation of the blake2 hash function☆25Updated 4 years ago
- ☆44Updated 3 years ago
- Verilog implementation of the SHA-512 hash function.☆39Updated 3 months ago
- Implementation of SHA256 Hasher with UART Transceiver in Verilog. Designed to run on Altera's DE2 FPGA Development Board.☆16Updated 6 years ago
- ☆19Updated 7 years ago
- DUAL Spartan6 Development Platform☆86Updated 7 years ago
- Maetti's Fork (Ethereum) + Altera/Intel OpenCL(FPGA)☆41Updated 4 years ago
- SQRL FK33 board files, example designs and scripts.☆17Updated 2 years ago
- Implementation of an RSA VDF evaluator targeting FPGAs.☆48Updated 5 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 5 years ago