Alternatives and similar repositories for gdscpp

Users that are interested in gdscpp are comparing it to the libraries listed below

• HomerReid / libGDSII
  C++ library and command-line utility for reading GDSII geometry files
  ☆51Updated 5 years ago
• EDDRSoftware / gdsFileParser
  This library is a low level parser for the GDSII file format.
  ☆35Updated 8 years ago
• ashtanyuk / GDSII-Links
  GDSII file format links
  ☆14Updated 5 years ago
• klayoutmatthias / dump_oas_gds2
  An OASIS and GDS2 (chip layout format) binary dump tool for debugging
  ☆45Updated 8 years ago
• rubenvanstaden / spira
  Parameterized verification framework (PCells, DRC, LVS) for Superconducting and Quantum Electronics.
  ☆18Updated 6 years ago
• purdue-onchip / gds2Para
  GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
  ☆128Updated 2 years ago
• klayoutmatthias / calibre2klayout
  A single-script repo for a script to turn a calibre layer file to a KLayout .lyp file
  ☆13Updated 7 years ago
• EDDRSoftware / oaFileParser
  This library is a low level parser for the OpenAccess file format.
  ☆15Updated 8 years ago
• skuep / GDS3D
  Fork from https://sourceforge.net/projects/gds3d
  ☆68Updated last year
• gdsfactory / skywater130
  skywater 130nm pdk
  ☆40Updated last week
• limbo018 / OpenMPL
  An open multiple patterning framework
  ☆81Updated last year
• jefftrull / EDASkel
  A skeleton EDA App in C++, featuring design data parsers (using Boost.Spirit), a basic GUI with Qt, a Tcl shell (with non-polling integra…
  ☆38Updated last year
• s94285 / SPICE
  A LTSPICE like circuit simulation software, base on Qt
  ☆28Updated 5 years ago
• rachelselinar / ReGDS-Logic-Gate-Extraction
  A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog …
  ☆32Updated last year
• cogenda / pyEDA
  A python framework for EDA applications.
  ☆37Updated 14 years ago
• ycchen218 / EDA-DRC-Prediction
  This is a deep-learning based model for Electronic Design Automation(EDA), predicting the Design Rule Check (DRC) violation location.
  ☆12Updated 2 years ago
• wrcad / xictools
  XicTools: Xic graphical editor, WRspice circuit simulator, and accessories. for electronic design.
  ☆178Updated last month
• s-holst / GDS2WebGL
  Translates GDSII into HTML/JS that can be viewed in WebGL-capable web browsers.
  ☆59Updated 5 years ago
• scholi / libgds
  Python library to handle GDS version 2 (GDS2 or GDSII) data
  ☆12Updated 7 years ago
• clin99 / awesome-eda
  ☆95Updated 6 years ago
• mattvenn / logo-to-gds2
  ☆18Updated 3 years ago
• ediloren / FastCap2
  FastCap is the premium capacitance solver originally developed at M.I.T. on Unix platform. A de-facto golden reference standard, FastCap …
  ☆50Updated 10 years ago
• Coloquinte / PlaceRoute
  VLSI placement and routing tool
  ☆15Updated 3 weeks ago
• libresilicon / magic-8.2
  Magic VLSI Layout Tool
  ☆21Updated 6 years ago
• peaclab / PACT
  PACT: A Parallel Compact Thermal Simulator
  ☆64Updated 3 months ago
• parallella / openeda
  Open source EDA chip design flow
  ☆51Updated 8 years ago
• paripath / cdf
  Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format
  ☆13Updated 5 years ago
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆57Updated last month
• Semi-ATE / Semi-ATE
  Semiconductor Automatic Test Equipment
  ☆57Updated 2 months ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆35Updated last month