Alternatives and similar repositories for FISC-VHDL

Users that are interested in FISC-VHDL are comparing it to the libraries listed below

• PacoReinaCampo / PU-RISCV
  Processing Unit with RISCV-32 / RISCV-64 / RISCV-128
  ☆20Updated last month
• karlfant / NCL_sandbox
  Is a collection of NULL Convention Logic (NCL) circuits and libraries written in Verilog to provide the experience of logically determine…
  ☆15Updated 9 years ago
• jerry-D / SYMPL-GP-GPU-Compute-Engines
  Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…
  ☆22Updated 6 years ago
• ultraembedded / altor32
  AltOr32 - Alternative Lightweight OpenRisc CPU
  ☆12Updated 9 years ago
• PacoReinaCampo / SoC-RISCV
  System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆22Updated last month
• jbush001 / MiteCPU
  Minimal microprocessor
  ☆20Updated 7 years ago
• sdasgup3 / parallel-processor-design
  Super scalar Processor design
  ☆21Updated 10 years ago
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆17Updated last year
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• PacoReinaCampo / vhdl2verilog
  Hardware Description Language Translator
  ☆17Updated last month
• franzflasch / leiwand_rv32
  RISC-V RV32I CPU written in verilog
  ☆10Updated 4 years ago
• mballance / fwrisc-s
  ☆10Updated 5 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆34Updated 8 years ago
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆76Updated 2 months ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆27Updated 3 years ago
• ZipCPU / videozip
  A ZipCPU SoC for the Nexys Video board supporting video functionality
  ☆18Updated 7 months ago
• mjkkirschner / simpleGPUCore
  verilog/FPGA hardware description for very simple GPU
  ☆17Updated 6 years ago
• armleo / ArmleoCPU
  ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set
  ☆6Updated 2 years ago
• Poofjunior / fpga_fast_serial_sort
  a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
  ☆40Updated 9 years ago
• freecores / theia_gpu
  Theia: ray graphic processing unit
  ☆20Updated 10 years ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆30Updated 6 months ago
• leos313 / DOOM_FPGA
  Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs
  ☆18Updated 5 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆42Updated 7 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆41Updated last year
• Vitorian / awesome-mpsoc
  Public resources available for Xilinx MPSOC+ and SDSOC hardware
  ☆18Updated 8 years ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated last month
• efabless / caravel-lite
  ☆17Updated 7 months ago
• openhwgroup / cv32e41p
  4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
  ☆27Updated last year
• freecores / sparc64soc
  OpenSPARC-based SoC
  ☆68Updated 10 years ago