primiano / tetris-vhdlLinks
A bare-metal pure hardware implementation of the Tetris game for FPGA
☆20Updated 8 years ago
Alternatives and similar repositories for tetris-vhdl
Users that are interested in tetris-vhdl are comparing it to the libraries listed below
Sorting:
- ☆17Updated 2 years ago
- SymbiFlow WIP changes for Yosys Open SYnthesis Suite☆39Updated last year
- YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…☆45Updated last year
- nextpnr portable FPGA place and route tool☆20Updated last year
- OSVVM UART Verification Components. Uart Transmitter with error injection for parity, stop, and break errors. UART Receiver verificati…☆13Updated this week
- Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs☆20Updated 5 years ago
- Project X-Ray Database: XC7 Series☆73Updated 4 years ago
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆38Updated last week
- Board and connector definition files for nMigen☆30Updated 5 years ago
- This is a higan/Verilator co-simulation example/framework☆51Updated 7 years ago
- FPGA Assembly (FASM) Parser and Generator☆99Updated 3 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆45Updated 3 years ago
- I2C controller core☆16Updated 3 years ago
- The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …☆51Updated 7 months ago
- RISC-V RV32I CPU written in verilog☆10Updated 5 years ago
- A wishbone controlled FM transmitter hack☆23Updated last year
- Free open source EDA tools☆66Updated 6 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆41Updated 10 years ago
- OpenRISC processor IP core based on Tomasulo algorithm☆34Updated 3 years ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated 2 months ago
- SPI core☆14Updated 6 years ago
- VexRiscv-SMP integration test with LiteX.☆26Updated 5 years ago
- OpenSPARC-based SoC☆74Updated 11 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- Verilog Language Extension for Visual Studio☆18Updated this week
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆19Updated last year
- Hardware-side component of Hastlayer for Microsoft Project Catapult FPGAs. See https://hastlayer.com for details.☆13Updated 5 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆31Updated 5 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆51Updated 10 years ago
- ☆24Updated 4 years ago