Python-based Portable IP-core Synthesis Framework for FPGA-based Computing
☆54Nov 21, 2016Updated 9 years ago
Alternatives and similar repositories for PyCoRAM
Users that are interested in PyCoRAM are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Veriloggen: A Mixed-Paradigm Hardware Construction Framework☆327Mar 8, 2026Updated 7 months ago
- Polyphony is Python based High-Level Synthesis compiler.☆110Apr 14, 2026Updated 6 months ago
- ☆43May 26, 2018Updated 8 years ago
- ☆56Jul 25, 2024Updated 2 years ago
- The Shang high-level synthesis framework☆120May 29, 2014Updated 12 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Rapid system integration of high-level synthesis kernels using the LEAP FPGA framework☆12Apr 17, 2016Updated 10 years ago
- IP-core package generator for AXI4/Avalon☆22Nov 25, 2018Updated 7 years ago
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆802Jun 15, 2024Updated 2 years ago
- Zynq PR Management☆13Apr 20, 2016Updated 10 years ago
- Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…☆109Jan 29, 2022Updated 4 years ago
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- Documentation for the entire CGRAFlow☆19Sep 17, 2021Updated 5 years ago
- Verilog netlist parser/database (derived from http://nldb.sourceforge.net)☆13Dec 12, 2014Updated 11 years ago
- Cross EDA Abstraction and Automation☆45Updated this week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- embedPythonInVerilogExample☆10Mar 23, 2017Updated 9 years ago
- Verification Utilities for MyHDL☆17Oct 26, 2023Updated 3 years ago
- A framework for FPGA emulation of mixed-signal systems☆39Jul 28, 2021Updated 5 years ago
- System Design in Python (SyDPy) is a tool for design and verification of concurrent systems. The tool is offered as an alternative to Sys…☆12Jun 2, 2016Updated 10 years ago
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆53Jan 13, 2021Updated 5 years ago
- Face Verification Example with Flower / Federated Learning☆12Apr 3, 2023Updated 3 years ago
- Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/)☆21Jan 15, 2016Updated 10 years ago
- A very simple UART implementation in MyHDL☆17Aug 21, 2014Updated 12 years ago
- Adding PR to the PYNQ Overlay☆19Apr 19, 2017Updated 9 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- The PE for the second generation CGRA (garnet).☆18Updated this week
- Core BriCA Version 1 code.☆17Apr 13, 2026Updated 6 months ago
- the actual epiphany backend☆20May 18, 2013Updated 13 years ago
- Polyhedral Compilation tool for High Level Synthesis.☆11May 13, 2014Updated 12 years ago
- ☆31Aug 8, 2020Updated 6 years ago
- RISC-V RV32I CPU written in verilog☆10Jul 11, 2020Updated 6 years ago
- iDEA FPGA Soft Processor☆17Jun 9, 2016Updated 10 years ago
- NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network☆367Oct 17, 2023Updated 3 years ago
- Learn, share and collaborate on ASIC design using open tools and technologies☆12Dec 27, 2020Updated 5 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- A library for generating Software Defined Radio-intended DSP code for FPGAs that makes use of the MyHDL (www.myhdl.org) Python library. T…☆25Aug 29, 2012Updated 14 years ago
- Bluespec H.264 Decoder☆12Jul 17, 2014Updated 12 years ago
- Combination of Analog Circuit Sizing and DL.☆18Mar 24, 2023Updated 3 years ago
- Parallel Array of Simple Cores. Multicore processor.☆101May 16, 2019Updated 7 years ago
- BitGPU is a GPU approach to solve the bitwidth optimization problem in FPGA datapaths.☆11Feb 10, 2017Updated 9 years ago
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 12 years ago
- RISC-V documentation transrate to Japanese.☆73Jan 1, 2022Updated 4 years ago