admk / soapLinks
soap - Structural Optimisation of Arithmetic Programs
☆24Updated 9 years ago
Alternatives and similar repositories for soap
Users that are interested in soap are comparing it to the libraries listed below
Sorting:
- firrtlator is a FIRRTL C++ library☆23Updated 8 years ago
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆56Updated 5 years ago
- An executable specification of the RISCV ISA in L3.☆41Updated 6 years ago
- Reference Hardware Implementations of Bit Extract/Deposit Instructions☆25Updated 8 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆37Updated 4 years ago
- Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python☆13Updated 4 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- Manythread RISC-V overlay for FPGA clusters☆38Updated last month
- Iodine: Verifying Constant-Time Execution of Hardware☆14Updated 4 years ago
- Exploration of alternative hardware description languages☆28Updated 7 years ago
- RISC-V instruction set CPUs in HardCaml☆15Updated 9 years ago
- ReconOS - Operating System for Reconfigurable Hardware☆29Updated 3 years ago
- ☆19Updated 10 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Updated 9 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆29Updated last week
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆75Updated 6 years ago
- Verilog AST☆21Updated last year
- An experimental System-on-Chip with a custom compiler toolchain.☆60Updated 5 years ago
- An online Verilog IDE based on YosysJS.☆24Updated 9 years ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- ☆29Updated 3 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 4 years ago
- Documentation for the BOOM processor☆47Updated 8 years ago
- An advanced automated reasoning tool for memory consistency model specifications.☆25Updated 3 years ago
- A Verilog parser for Haskell.☆36Updated 4 years ago
- Multi-threaded 32-bit embedded core family.☆24Updated 13 years ago
- A scala based simulator for circuits described by a LoFirrtl file☆49Updated 2 years ago
- An LLVM based mini-C to Verilog High-level Synthesis tool☆39Updated 8 months ago