Alternatives and similar repositories for soap

Users that are interested in soap are comparing it to the libraries listed below

• SiliconSemantics / firrtlator
  firrtlator is a FIRRTL C++ library
  ☆23Updated 9 years ago
• jameshegarty / rigel
  Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…
  ☆56Updated 5 years ago
• SRI-CSL / l3riscv
  An executable specification of the RISCV ISA in L3.
  ☆42Updated 6 years ago
• cliffordwolf / bextdep
  Reference Hardware Implementations of Bit Extract/Deposit Instructions
  ☆24Updated 8 years ago
• ReconOS / reconos
  ReconOS - Operating System for Reconfigurable Hardware
  ☆29Updated 3 years ago
• daniellustig / pipecheck
  ☆19Updated 10 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆38Updated 4 years ago
• gokhankici / iodine
  Iodine: Verifying Constant-Time Execution of Hardware
  ☆15Updated 4 years ago
• ujamjar / hardcaml-riscv
  RISC-V instruction set CPUs in HardCaml
  ☆15Updated 9 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated 2 years ago
• vegaluisjose / vast
  Verilog AST
  ☆21Updated 2 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• cfelton / alt.hdl
  Exploration of alternative hardware description languages
  ☆28Updated 7 years ago
• rsnikhil / Bluespec_BSV_Formal_Semantics
  Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document
  ☆18Updated 9 years ago
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆50Updated 8 years ago
• tomahawkins / verilog
  A Verilog parser for Haskell.
  ☆36Updated 4 years ago
• maerhart / llhd
  A low-level intermediate representation for hardware description languages
  ☆28Updated 5 years ago
• etherzhhb / Shang
  The Shang high-level synthesis framework
  ☆120Updated 11 years ago
• cornell-brg / pydgin
  A (Py)thon (D)SL for (G)enerating (In)struction set simulators.
  ☆167Updated 7 years ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆29Updated 3 years ago
• ymanerka / rtlcheck
  RTLCheck
  ☆23Updated 7 years ago
• laforest / Octavo
  Verilog FPGA Parts Library. Old Octavo soft-CPU project.
  ☆75Updated 6 years ago
• David-Durst / embeddedHaskellAetherling
  ☆30Updated 3 years ago
• udif / ctoverilog
  A C to verilog compiler
  ☆52Updated 10 years ago
• soarlab / FPTuner
  Rigorous Floating-Point Mixed-Precision Tuner
  ☆16Updated 5 years ago
• David-Durst / aetherling
  Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python
  ☆13Updated 4 years ago
• ted-xie / REAPR
  REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…
  ☆16Updated 6 years ago
• combinatorylogic / soc
  An experimental System-on-Chip with a custom compiler toolchain.
  ☆60Updated 5 years ago
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆32Updated 4 years ago
• foshardware / lsc
  Libre Silicon Compiler
  ☆22Updated 4 years ago