admk / soapLinks
soap - Structural Optimisation of Arithmetic Programs
☆24Updated 9 years ago
Alternatives and similar repositories for soap
Users that are interested in soap are comparing it to the libraries listed below
Sorting:
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆56Updated 5 years ago
- firrtlator is a FIRRTL C++ library☆23Updated 9 years ago
- An executable specification of the RISCV ISA in L3.☆42Updated 6 years ago
- Reference Hardware Implementations of Bit Extract/Deposit Instructions☆24Updated 8 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆38Updated 4 years ago
- RTLCheck☆24Updated 7 years ago
- ☆19Updated 11 years ago
- Iodine: Verifying Constant-Time Execution of Hardware☆15Updated 4 years ago
- Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python☆13Updated 4 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- ☆30Updated 3 years ago
- An online Verilog IDE based on YosysJS.☆24Updated 10 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- An advanced automated reasoning tool for memory consistency model specifications.☆25Updated 4 years ago
- Liveness-driven random C code generator☆42Updated 5 months ago
- Rigorous Floating-Point Mixed-Precision Tuner☆16Updated 5 years ago
- Verilog AST☆21Updated 2 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 6 years ago
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Updated 9 years ago
- ReconOS - Operating System for Reconfigurable Hardware☆29Updated 3 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆76Updated 6 years ago
- Manythread RISC-V overlay for FPGA clusters☆39Updated 4 months ago
- RISC-V instruction set CPUs in HardCaml☆15Updated 9 years ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 4 years ago
- A SAT solver implementation in VHDL, team tussle☆21Updated 9 years ago
- COATCheck☆13Updated 7 years ago
- The PE for the second generation CGRA (garnet).☆18Updated 8 months ago
- REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…☆16Updated 6 years ago
- A multicore microprocessor test harness for measuring interference☆14Updated 5 years ago