Alternatives and similar repositories for ImageDetectionHW2

Users that are interested in ImageDetectionHW2 are comparing it to the libraries listed below

• fixstars / ultra96_design
  Repository of HW design and SW for Ultra96 board + MIPI board
  ☆17Updated 6 years ago
• nikkatsa7 / HOG_Zedboard
  A real time Histogram of Oriented Gradients Implementation on FPGA
  ☆32Updated 6 years ago
• ikwzm / ZynqMP-FPGA-Ubuntu18.04-Ultra96
  Ubuntu 18.04 Desktop for Ultra96/Ultra96-V2
  ☆19Updated 5 years ago
• ikwzm / ZynqMP-FPGA-Linux
  FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq Ultrascale+ MPSoC)
  ☆130Updated last year
• Digilent / Petalinux-Zybo-Z7-20
  ☆53Updated 2 years ago
• AEW2015 / PYNQ_PR_Overlay
  Adding PR to the PYNQ Overlay
  ☆17Updated 8 years ago
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆55Updated 5 years ago
• PeterOgden / overlay_tutorial
  Premade bitstreams and block designs to complemented the PYNQ overlay tutorial
  ☆40Updated 3 years ago
• hellgate202 / csi2_rx
  MIPI CSI-2 RX
  ☆32Updated 3 years ago
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆105Updated 7 years ago
• Digilent / Zybo-Z7-20-pcam-5c
  ☆56Updated 2 years ago
• gtaylormb / ultra96v2_imx219_to_displayport
  Raspberry Pi v2 camera (IMX219) to DisplayPort of Ultra96-V2 board through PL
  ☆70Updated 3 years ago
• andrewandrepowell / zybo_petalinux_video_hls
  Demonstration of a video processing design for the Digilent Zybo, using Web Camera for input and VGA interface for output.
  ☆25Updated 8 years ago
• gewuek / vitis_ai_custom_platform_flow
  This project is trying to create a base vitis platform to run with DPU
  ☆47Updated 4 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 9 years ago
• Xilinx / PYNQ-BOT
  ☆29Updated 7 years ago
• mpccelon / hardware-accelerated-hog-svm
  HOG-SVM algorithm implemented in a Zynq 7000 SoC (Digilent ZYBO)
  ☆15Updated 7 years ago
• fixstars / xg_mac
  10G Ethernet MAC implementation
  ☆21Updated 4 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆58Updated 5 years ago
• Xilinx / kria-vitis-platforms
  Kria Vitis platforms and overlays
  ☆102Updated last month
• Xilinx / GO-PYNQ
  Xilinx Contest Kshitij 2019
  ☆19Updated 2 years ago
• bmartini / verilog-arbiter
  A look ahead, round-robing parametrized arbiter written in Verilog.
  ☆42Updated 5 years ago
• Avnet / Ultra96-PYNQ
  Board files to build Ultra 96 PYNQ image
  ☆155Updated 6 months ago
• sumilao / Zynq-7000-DPU-TRD
  Zynq-7000 DPU TRD
  ☆45Updated 5 years ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆73Updated last year
• DreamIP / haddoc2
  Caffe to VHDL
  ☆67Updated 5 years ago
• sammy17 / vivado_hls_tutorial
  Source code of basic Xilinx Vivado HLS image processing tutorial using HLS openCV functions
  ☆25Updated 6 years ago
• Xilinx / PYNQ-HelloWorld
  This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.
  ☆104Updated 2 years ago
• parimalp / Advanced-Embedded-System-Design-Flow-on-Zynq
  ☆18Updated 6 years ago
• sopynq / huffman-encoding-core
  Huffman encoding core (Vivado HLS Project)
  ☆12Updated 5 years ago