NNgen / nngen
NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
☆351Updated last year
Alternatives and similar repositories for nngen:
Users that are interested in nngen are comparing it to the libraries listed below
- Veriloggen: A Mixed-Paradigm Hardware Construction Framework☆315Updated 9 months ago
- Binary Neural Network Framework for FPGA(Differentiable LUT)☆158Updated 5 months ago
- DPU on PYNQ☆219Updated last year
- Polyphony is Python based High-Level Synthesis compiler.☆104Updated 3 months ago
- Dataflow QNN inference accelerator examples on FPGAs☆213Updated last month
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆417Updated 5 years ago
- RISC-V Integration for PYNQ☆171Updated 5 years ago
- Code generation tool for control and status registers☆381Updated 2 months ago
- GUINNESS: A GUI-based binarized deep Neural NEtwork SyntheSizer toward an FPGA☆180Updated 5 years ago
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆354Updated 7 years ago
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆270Updated 5 years ago
- Network on Chip Implementation written in SytemVerilog☆174Updated 2 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆339Updated 3 months ago
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆707Updated 10 months ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆104Updated 7 years ago
- magma circuits☆260Updated 6 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆488Updated 2 months ago
- Board files to build Ultra 96 PYNQ image☆154Updated 4 months ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆209Updated 5 years ago
- IC implementation of Systolic Array for TPU☆235Updated 6 months ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆268Updated 2 weeks ago
- Vitis HLS Library for FINN☆193Updated this week
- ☆118Updated 3 years ago
- ☆92Updated 10 months ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆318Updated 3 months ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆190Updated 4 years ago
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆409Updated this week
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆369Updated this week
- Common SystemVerilog components☆614Updated this week
- Ariane is a 6-stage RISC-V CPU☆135Updated 5 years ago