Alternatives and similar repositories for nngen:

Users that are interested in nngen are comparing it to the libraries listed below

• PyHDI / veriloggen
  Veriloggen: A Mixed-Paradigm Hardware Construction Framework
  ☆312Updated 7 months ago
• ryuz / BinaryBrain
  Binary Neural Network Framework for FPGA(Differentiable LUT)
  ☆155Updated 4 months ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆171Updated 2 years ago
• phanrahan / magma
  magma circuits
  ☆259Updated 5 months ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆375Updated last month
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆461Updated last month
• PyHDI / Pyverilog
  Python-based Hardware Design Processing Toolkit for Verilog HDL
  ☆690Updated 9 months ago
• bu-icsg / dana
  Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
  ☆210Updated 5 years ago
• drichmond / RISC-V-On-PYNQ
  RISC-V Integration for PYNQ
  ☆170Updated 5 years ago
• chipsalliance / chisel-template
  A template project for beginning new Chisel work
  ☆624Updated last month
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆214Updated last year
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆207Updated 5 months ago
• ridecore / ridecore
  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
  ☆344Updated 7 years ago
• polyphony-dev / polyphony
  Polyphony is Python based High-Level Synthesis compiler.
  ☆103Updated last month
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆191Updated 2 weeks ago
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆363Updated 2 weeks ago
• pymtl / pymtl3
  Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
  ☆407Updated 2 weeks ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools
  ☆163Updated last month
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆265Updated 4 months ago
• IBM / AccDNN
  A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
  ☆414Updated 5 years ago
• jofrfu / tinyTPU
  Implementation of a Tensor Processing Unit for embedded systems and the IoT.
  ☆449Updated 6 years ago
• fpgasystems / spooNN
  FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)
  ☆266Updated 5 years ago
• Xilinx / finn-examples
  Dataflow QNN inference accelerator examples on FPGAs
  ☆209Updated this week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆593Updated last week
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆412Updated last week
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆189Updated 2 weeks ago
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆308Updated this week
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆245Updated last year
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆268Updated last week
• SingularityKChen / dl_accelerator
  Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
  ☆186Updated 4 years ago