Alternatives and similar repositories for nngen

Users that are interested in nngen are comparing it to the libraries listed below

• PyHDI / veriloggen
  Veriloggen: A Mixed-Paradigm Hardware Construction Framework
  ☆321Updated last year
• ryuz / BinaryBrain
  Binary Neural Network Framework for FPGA(Differentiable LUT)
  ☆162Updated 2 months ago
• IBM / AccDNN
  A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
  ☆431Updated 5 years ago
• Avnet / Ultra96-PYNQ
  Board files to build Ultra 96 PYNQ image
  ☆157Updated last month
• Xilinx / logicnets
  Train and deploy LUT-based neural networks on FPGAs
  ☆99Updated last year
• polyphony-dev / polyphony
  Polyphony is Python based High-Level Synthesis compiler.
  ☆108Updated 8 months ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆191Updated 3 years ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆532Updated last month
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆228Updated 2 months ago
• drichmond / RISC-V-On-PYNQ
  RISC-V Integration for PYNQ
  ☆176Updated 6 years ago
• HirokiNakahara / FPGA_lecture
  Source Codes for a lecture entitled "Parallel and Reconfigurable VLSI Computing" in Tokyo Tech.
  ☆28Updated 4 years ago
• ridecore / ridecore
  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
  ☆363Updated 8 years ago
• phanrahan / magma
  magma circuits
  ☆262Updated last year
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆385Updated this week
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆284Updated last week
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆341Updated this week
• HirokiNakahara / GUINNESS
  GUINNESS: A GUI-based binarized deep Neural NEtwork SyntheSizer toward an FPGA
  ☆181Updated 6 years ago
• jofrfu / tinyTPU
  Implementation of a Tensor Processing Unit for embedded systems and the IoT.
  ☆509Updated 6 years ago
• Xilinx / PYNQ-HelloWorld
  This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.
  ☆106Updated 2 years ago
• bu-icsg / dana
  Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
  ☆215Updated 5 years ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆427Updated last month
• definelicht / hlslib
  A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
  ☆329Updated 9 months ago
• pymtl / pymtl3
  Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
  ☆431Updated last month
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆107Updated 7 years ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆208Updated 2 weeks ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆294Updated last week
• chipsalliance / silicon-notebooks
  ☆172Updated 2 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆228Updated last week
• SingularityKChen / dl_accelerator
  Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
  ☆201Updated 5 years ago
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆268Updated this week