Alternatives and similar repositories for nngen

Users that are interested in nngen are comparing it to the libraries listed below

• PyHDI / veriloggen
  Veriloggen: A Mixed-Paradigm Hardware Construction Framework
  ☆324Updated last year
• ryuz / BinaryBrain
  Binary Neural Network Framework for FPGA(Differentiable LUT)
  ☆171Updated 5 months ago
• Avnet / Ultra96-PYNQ
  Board files to build Ultra 96 PYNQ image
  ☆157Updated 4 months ago
• Xilinx / logicnets
  Train and deploy LUT-based neural networks on FPGAs
  ☆106Updated last year
• drichmond / RISC-V-On-PYNQ
  RISC-V Integration for PYNQ
  ☆180Updated 6 years ago
• phanrahan / magma
  magma circuits
  ☆264Updated last year
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆239Updated 5 months ago
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆292Updated 3 months ago
• pymtl / pymtl3
  Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
  ☆442Updated 5 months ago
• polyphony-dev / polyphony
  Polyphony is Python based High-Level Synthesis compiler.
  ☆108Updated last year
• Xilinx / PYNQ-HelloWorld
  This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.
  ☆107Updated 3 years ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆561Updated 3 months ago
• jofrfu / tinyTPU
  Implementation of a Tensor Processing Unit for embedded systems and the IoT.
  ☆537Updated 7 years ago
• IBM / AccDNN
  A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
  ☆437Updated 6 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆197Updated 3 years ago
• Xilinx / HLS
  Vitis HLS LLVM source code and examples
  ☆403Updated 4 months ago
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆107Updated 7 years ago
• definelicht / hlslib
  A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
  ☆334Updated last year
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆355Updated last week
• rggen / rggen
  Code generation tool for control and status registers
  ☆441Updated 3 weeks ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆213Updated 3 weeks ago
• Xilinx / Vitis-In-Depth-Tutorial
  ☆117Updated 4 years ago
• ridecore / ridecore
  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
  ☆371Updated 8 years ago
• Xilinx / XilinxBoardStore
  ☆312Updated last week
• UCSBarchlab / PyRTL
  A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Si…
  ☆294Updated 2 months ago
• Xilinx / finn-examples
  Dataflow QNN inference accelerator examples on FPGAs
  ☆241Updated 5 months ago
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆400Updated 3 months ago
• spcl / gemm_hls
  Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
  ☆374Updated last year
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆279Updated last month
• bu-icsg / dana
  Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
  ☆221Updated 6 years ago