An agentic context evolution approach for RTL coding
☆48Sep 20, 2026Updated last month
Alternatives and similar repositories for ACE-RTL
Users that are interested in ACE-RTL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆10Sep 29, 2024Updated 2 years ago
- [ICCAD'26] Forbench: Symbolic Simulation Helps Make Your Testbench More Formal☆15Updated this week
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 3 years ago
- EvolveGen: Algorithmic Level Hardware Model Checking Benchmark Generation through Reinforcement Learning (TACAS 2026)☆10Oct 9, 2025Updated last year
- A high-efficiency hybrid solving CEC algorithm☆14May 25, 2023Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A fork of the Kissat SAT solver with additional features. Supports incremental solving.☆17Aug 13, 2022Updated 4 years ago
- ☆13Jan 20, 2023Updated 3 years ago
- ☆19Dec 21, 2020Updated 5 years ago
- E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis (DAC2025)☆33Jun 23, 2025Updated last year
- BTOR2 MLIR project☆26Jan 17, 2024Updated 2 years ago
- Equivalence Verification Checking for Code Transformation via Equality Saturation☆13Jun 1, 2026Updated 5 months ago
- APS: An open-source toolchain towards agile processor specialization based on MLIR☆23Updated this week
- DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction (ASP-DAC 2024)☆14Nov 2, 2023Updated 3 years ago
- RTLScout is a agentic RTL optimization framework☆70Nov 3, 2026Updated last week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆35Aug 25, 2024Updated 2 years ago
- Automatic generation of architecture-level models for hardware from its RTL design.☆17Apr 12, 2023Updated 3 years ago
- LLM4HWDesign Starting Toolkit☆20Oct 4, 2024Updated 2 years ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆46Apr 3, 2025Updated last year
- benchmarks for hls equivalence checking☆11Nov 22, 2022Updated 3 years ago
- PRO-V: An Efficient Program Generation Multi-Agent System for Automatic RTL Verification☆36Dec 11, 2025Updated 10 months ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆30Apr 9, 2025Updated last year
- ☆21Nov 2, 2026Updated last week
- GPU kernel verification with Pulse☆29Updated this week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆256Jun 8, 2026Updated 5 months ago
- Certify Model Checking Witnesses in AIGER☆14Updated this week
- easter egg is a flexible, high-performance e-graph library with support of multiple additional assumptions at once☆14Mar 27, 2025Updated last year
- A framework for building hardware verification platform using software method☆41Oct 30, 2026Updated last week
- Yosys RTLIL dialect for MLIR☆25Jun 12, 2025Updated last year
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025, ACM TODAES 2026)☆53Jul 22, 2026Updated 3 months ago
- Translate Chisel hardware design code to Scala simulation code.☆15May 15, 2025Updated last year
- Cell Layout Generation for DTCO/STCO Exploration Toolkit☆36May 24, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆10Jan 9, 2026Updated 10 months ago
- ☆15Dec 6, 2023Updated 2 years ago
- ☆14Jan 3, 2018Updated 8 years ago
- Collection of utlities for writing parsers. Includes a fast DIMACS CNF parser.☆15Nov 19, 2024Updated last year
- CODO: An Automated Compiler for Comprehensive Dataflow Optimization☆41Updated this week
- C++ implementation of FRAIGs. Won the 1st place in 2018 Cadence-sponsored contest in NTU DSnP.☆10Oct 21, 2020Updated 6 years ago
- Formal verification tools for Chisel and RISC-V☆15Mar 29, 2026Updated 7 months ago
Are these results useful?