Verified Verilog Equivalence checker, written and verified in Coq.
☆15Oct 20, 2026Updated 3 weeks ago
Alternatives and similar repositories for Vera
Users that are interested in Vera are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A DSL for formal verification of hardware and software systems using Rocq/Coq.☆13Updated this week
- A Lean-embedded framework to verify Verilog modules☆17Oct 6, 2026Updated last month
- Translate Chisel hardware design code to Scala simulation code.☆15May 15, 2025Updated last year
- A collection of datapath circuit design and verification benchmarks☆19Aug 24, 2026Updated 2 months ago
- A digital circuit verification library for Lean4☆12Jul 29, 2026Updated 3 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A tool to connect SMT-based frontends to Lean4.☆21Nov 3, 2026Updated last week
- ☆15Jul 9, 2026Updated 4 months ago
- Rocq framework to define the semantics of CPU architectures☆41Updated this week
- ☆11Sep 16, 2026Updated last month
- easter egg is a flexible, high-performance e-graph library with support of multiple additional assumptions at once☆14Mar 27, 2025Updated last year
- A tool for formally verifying constant-time software against hardware 🕰️☆17Feb 1, 2025Updated last year
- A codebase accompanying the paper "Improving Performance Estimation for FPGA-based Accelerators for Convolutional Neural Networks", by Fe…☆13May 27, 2020Updated 6 years ago
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Aug 22, 2021Updated 5 years ago
- ☆13Oct 25, 2026Updated 2 weeks ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Course material for "Automation of Logical Reasoning"☆10May 26, 2025Updated last year
- BTOR2 MLIR project☆26Jan 17, 2024Updated 2 years ago
- ☆14May 7, 2026Updated 6 months ago
- A tool to generate optimized hardware files for univariate functions.☆14Sep 5, 2024Updated 2 years ago
- Verilog development and verification project for HOL4☆28Apr 25, 2025Updated last year
- Tools for reasoning about circuits in Rosette/Racket 🔌☆20Feb 1, 2025Updated last year
- Tools for manipulating CHC and related files☆15Apr 21, 2023Updated 3 years ago
- Easy SMT solver interaction☆37Feb 3, 2026Updated 9 months ago
- A mutual induction tactic for Lean 4.☆33Oct 29, 2026Updated last week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ARCHIE is a QEMU-based architecture-independent fault evaluation tool, that is able to simulate transient and permanent instruction and d…☆37Mar 13, 2026Updated 7 months ago
- 💤 Relaxation labelling to refine edge detection 💤☆11Jul 29, 2019Updated 7 years ago
- ☆13Jun 18, 2025Updated last year
- Code for the paper "LLM Meets Bounded Model Checking: Neuro-symbolic Loop Invariant Inference" at ASE 2024☆31Sep 3, 2024Updated 2 years ago
- APS: An open-source toolchain towards agile processor specialization based on MLIR☆23Updated this week
- ☆32Nov 2, 2025Updated last year
- A type-safe, formally verifiable HDL compiler in Lean 4. Inspired by Clash, built for high-assurance hardware synthesis.☆174Updated this week
- Yosys RTLIL dialect for MLIR☆25Jun 12, 2025Updated last year
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆101Jan 29, 2026Updated 9 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Verified graph rewriting (for dataflow circuits).☆29Oct 29, 2026Updated last week
- A multicore microprocessor test harness for measuring interference☆15Apr 16, 2020Updated 6 years ago
- Formal verification tools for Chisel and RISC-V☆15Mar 29, 2026Updated 7 months ago
- Coinductive Interaction Trees in Lean4 using QPFs☆20Oct 18, 2026Updated 3 weeks ago
- FYP on using e-graphs to solve smt bitvector problems☆16Jun 24, 2025Updated last year
- ☆52Updated this week
- A Platform for High-Level Parametric Hardware Specification and its Modular Verification☆173Sep 17, 2026Updated last month
Are these results useful?