Replace Tcl scripting with Python
☆18Aug 25, 2026Updated this week
Alternatives and similar repositories for notcl
Users that are interested in notcl are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Learn, share and collaborate on ASIC design using open tools and technologies☆12Dec 27, 2020Updated 5 years ago
- Template Verilator project for beginners☆13Feb 2, 2023Updated 3 years ago
- CoreSmith is a Prompt to GDS Agentic Flow☆37Updated this week
- ☆23Aug 11, 2026Updated 2 weeks ago
- Filelist generator☆21Aug 11, 2026Updated 2 weeks ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- PyCacheGen: A Highly Configurable Open-Source Generator for Synthesizable Caches☆18Dec 14, 2025Updated 8 months ago
- Build infrastructure for class-wide tapeout for 18-224/624 Intro to Open Source Chip Design, Spring 2023☆21Aug 10, 2023Updated 3 years ago
- An open silicon CHERIoT Ibex microcontroller chip☆19May 23, 2025Updated last year
- Tool for generating multi-purpose makefiles for FPGA projects (clone of hdlmake from CERN)☆18Aug 16, 2021Updated 5 years ago
- ☆13Apr 15, 2025Updated last year
- RTLMeter benchmark suite☆32Updated this week
- A tool for cross-checking Verilog compilers☆15Apr 16, 2025Updated last year
- 10GbE XGMII TCP/IPv4 packet generator in C, co-simulating with Verilog, SystemVerilog and VHDL☆29Jan 28, 2025Updated last year
- ☆30Jul 27, 2017Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A Formal Verification Methodology to lower the adoption barriers for Formal Verification of ASIC and FPGA designs in the Space sector (th…☆25Jun 29, 2026Updated 2 months ago
- Testing Ibex build using Yosys and open source toolchains.☆11Oct 2, 2021Updated 4 years ago
- ☆13Dec 23, 2022Updated 3 years ago
- Open-source IPs Package Manager (IPM)☆16Feb 24, 2025Updated last year
- An open-source HDL register code generator fast enough to run in real time.☆91Aug 10, 2026Updated 3 weeks ago
- OpenCL version of Kaktwoos; Mine cacti with 0xA presses☆10Jun 16, 2022Updated 4 years ago
- EDA Analytics Central☆16Dec 8, 2022Updated 3 years ago
- Website for the OpenROAD tutorial held at the MICRO 2022 conference☆36Oct 6, 2022Updated 3 years ago
- Characterizer☆39Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Agile Hardware Design Course☆16Aug 15, 2026Updated 2 weeks ago
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆21Nov 13, 2024Updated last year
- An infrastructure for integrated EDA☆44Jul 20, 2023Updated 3 years ago
- FPGA 2025 SAT Accel: A modern SAT Solver on FPGA Repository☆14Mar 13, 2025Updated last year
- Next generation CGRA generator☆119Updated this week
- All In One Script Installer for Rabbit Sky☆11Nov 13, 2021Updated 4 years ago
- Collection of my userscripts for MusicBrainz☆14Aug 23, 2026Updated last week
- A Rocket-based RISC-V superscalar in-order core☆42Updated this week
- TAIDL: Tensor Accelerator ISA Definition Language☆19Apr 28, 2026Updated 4 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Differentiable Combinatorial Scheduling at Scale (ICML'24). Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu.☆24Oct 31, 2024Updated last year
- ☆18Feb 25, 2026Updated 6 months ago
- A collection of datapath circuit design and verification benchmarks☆19Aug 24, 2026Updated last week
- RISC-V Double Trap Fast-Track Extension☆15Mar 10, 2026Updated 5 months ago
- A Verilog AMBA AHB Multilayer interconnect generator☆13Aug 8, 2017Updated 9 years ago
- PROTON - A Python Framework for Physics-Based Electromigration Assessment on Contemporary VLSI Power Grids☆19Sep 10, 2024Updated last year
- Audio Signal Processing SoC☆20Mar 13, 2018Updated 8 years ago