sudhamshu091 / 32-Verilog-Mini-Projects
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 7…
☆666Updated 5 months ago
Alternatives and similar repositories for 32-Verilog-Mini-Projects:
Users that are interested in 32-Verilog-Mini-Projects are comparing it to the libraries listed below
- AMBA bus lecture material☆428Updated 5 years ago
- Verilog UART☆474Updated last month
- Implementation of CNN using Verilog☆212Updated 7 years ago
- Verilog AXI components for FPGA implementation☆1,692Updated last month
- Awesome ASIC design verification☆293Updated 3 years ago
- AMBA AXI VIP☆394Updated 9 months ago
- Contains the code examples from The UVM Primer Book sorted by chapters.☆526Updated 3 years ago
- Image Processing Toolbox in Verilog using Basys3 FPGA☆197Updated last year
- A DDR3 memory controller in Verilog for various FPGAs☆441Updated 3 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆326Updated 11 months ago
- This is a repository containing solutions to the problem statements given in HDL Bits website.☆348Updated last year
- Verilog I2C interface for FPGA implementation☆602Updated last month
- Verilog AXI stream components for FPGA implementation☆796Updated last month
- training labs and examples☆418Updated 2 years ago
- Various HDL (Verilog) IP Cores☆776Updated 3 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,256Updated 2 weeks ago
- Must-have verilog systemverilog modules☆1,762Updated 2 weeks ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆120Updated last year
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆120Updated 3 years ago
- SPI Master for FPGA - VHDL and Verilog☆280Updated last year
- 100 Days of RTL☆363Updated 8 months ago
- Reference examples and short projects using UVM Methodology☆265Updated 2 years ago
- automatic-verilog based on vimscript☆260Updated last year
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆201Updated last year
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆199Updated last year
- ☆264Updated last year
- Verilog PCI express components☆1,272Updated last year
- Verilog SDRAM memory controller☆326Updated 7 years ago
- The UVM written in Python☆422Updated last week
- uvm AXI BFM(bus functional model)☆244Updated 11 years ago