sudhamshu091 / 32-Verilog-Mini-Projects
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 7…
☆623Updated 3 months ago
Alternatives and similar repositories for 32-Verilog-Mini-Projects:
Users that are interested in 32-Verilog-Mini-Projects are comparing it to the libraries listed below
- AMBA bus lecture material☆407Updated 5 years ago
- Verilog UART☆451Updated this week
- Implementation of CNN using Verilog☆207Updated 7 years ago
- This is a repository containing solutions to the problem statements given in HDL Bits website.☆343Updated last year
- Awesome ASIC design verification☆286Updated 3 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆108Updated last year
- Contains the code examples from The UVM Primer Book sorted by chapters.☆513Updated 3 years ago
- Image Processing Toolbox in Verilog using Basys3 FPGA☆189Updated last year
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆307Updated 10 months ago
- AMBA AXI VIP☆382Updated 8 months ago
- 100 Days of RTL☆349Updated 6 months ago
- Verilog AXI components for FPGA implementation☆1,624Updated this week
- Verilog AXI stream components for FPGA implementation☆780Updated this week
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆117Updated 3 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆420Updated 3 years ago
- Verilog I2C interface for FPGA implementation☆581Updated this week
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆191Updated last year
- ☆258Updated last year
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,220Updated this week
- SPI Master for FPGA - VHDL and Verilog☆271Updated last year
- Various HDL (Verilog) IP Cores☆745Updated 3 years ago
- automatic-verilog based on vimscript☆252Updated last year
- Reference examples and short projects using UVM Methodology☆258Updated 2 years ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆135Updated 4 years ago
- Verilog PCI express components☆1,231Updated 10 months ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆164Updated 6 years ago
- 数字IC秋招项目、手撕代码☆34Updated 10 months ago
- 在vscode上的数字设计开发插件☆353Updated 2 years ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆563Updated 6 years ago
- 5-stage pipelined 32-bit MIPS microprocessor in Verilog☆120Updated 4 years ago