sudhamshu091 / 32-Verilog-Mini-Projects
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 7…
☆579Updated 3 months ago
Related projects ⓘ
Alternatives and complementary repositories for 32-Verilog-Mini-Projects
- AMBA bus lecture material☆375Updated 4 years ago
- Awesome ASIC design verification☆258Updated 2 years ago
- Image Processing Toolbox in Verilog using Basys3 FPGA☆183Updated last year
- Implementation of CNN using Verilog☆185Updated 7 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆93Updated 9 months ago
- training labs and examples☆397Updated 2 years ago
- Verilog UART☆418Updated last year
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,095Updated this week
- 100 Days of RTL☆332Updated 2 months ago
- Contains the code examples from The UVM Primer Book sorted by chapters.☆483Updated 2 years ago
- Reference examples and short projects using UVM Methodology☆254Updated 2 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆258Updated 6 months ago
- This is a repository containing solutions to the problem statements given in HDL Bits website.☆326Updated last year
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆110Updated 3 years ago
- AMBA AXI VIP☆361Updated 4 months ago
- Verilog AXI stream components for FPGA implementation☆738Updated 3 months ago
- synthesiseable ieee 754 floating point library in verilog☆527Updated last year
- Verilog AXI components for FPGA implementation☆1,499Updated 11 months ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆152Updated 6 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆171Updated last year
- This is the main repository for all the examples for the book Practical UVM☆170Updated 4 years ago
- Various HDL (Verilog) IP Cores☆707Updated 3 years ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆549Updated 6 years ago
- Common SystemVerilog components☆513Updated this week
- lowRISC Style Guides☆369Updated last month
- A DDR3 memory controller in Verilog for various FPGAs☆363Updated 3 years ago
- 数字IC秋招项目、手撕代码☆33Updated 6 months ago
- uvm AXI BFM(bus functional model)☆233Updated 11 years ago
- Verilog I2C interface for FPGA implementation☆543Updated 3 months ago
- Single Cycle MIPS Pipelined Processor using Verilog☆13Updated 3 years ago