sudhamshu091 / 32-Verilog-Mini-Projects

Related projects ⓘ

Alternatives and complementary repositories for 32-Verilog-Mini-Projects

• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆379Updated 4 years ago
• viduraakalanka / HDL-Bits-Solutions
  This is a repository containing solutions to the problem statements given in HDL Bits website.
  ☆330Updated last year
• Gowtham1729 / Image-Processing
  Image Processing Toolbox in Verilog using Basys3 FPGA
  ☆183Updated last year
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,113Updated this week
• raulbehl / 100DaysOfRTL
  100 Days of RTL
  ☆335Updated 3 months ago
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆266Updated 2 years ago
• alexforencich / verilog-uart
  Verilog UART
  ☆424Updated last year
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,518Updated 11 months ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆363Updated 4 months ago
• AniketBadhan / Convolutional-Neural-Network
  Implementation of CNN using Verilog
  ☆187Updated 7 years ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆745Updated 3 months ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆264Updated 6 months ago
• seldridge / verilog
  Repository for basic (and not so basic) Verilog blocks with high re-use potential
  ☆550Updated 6 years ago
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆398Updated 2 years ago
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆96Updated 9 months ago
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆483Updated 2 years ago
• VerificationExcellence / UVMReference
  Reference examples and short projects using UVM Methodology
  ☆254Updated 2 years ago
• vipinkmenon / neuralNetwork
  ☆244Updated 8 months ago
• HonkW93 / automatic-verilog
  automatic-verilog based on vimscript
  ☆239Updated last year
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆171Updated last year
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆111Updated 3 years ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆371Updated 2 months ago
• pConst / basic_verilog
  Must-have verilog systemverilog modules
  ☆1,656Updated 2 weeks ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆547Updated 4 months ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆710Updated 3 years ago
• WalkerLau / DetectHumanFaces
  Real time face detection based on Arm Cortex-M3 DesignStart and FPGA
  ☆189Updated last year
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆865Updated 3 years ago
• QShen3 / CNN-FPGA
  使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用
  ☆496Updated 6 years ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆518Updated this week
• xiaop1 / Verilog-Practice
  HDLBits website practices & solutions
  ☆691Updated 10 months ago