sudhamshu091 / 32-Verilog-Mini-ProjectsLinks
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 7…
☆711Updated 7 months ago
Alternatives and similar repositories for 32-Verilog-Mini-Projects
Users that are interested in 32-Verilog-Mini-Projects are comparing it to the libraries listed below
Sorting:
- AMBA bus lecture material☆441Updated 5 years ago
- Implementation of CNN using Verilog☆218Updated 7 years ago
- Verilog AXI stream components for FPGA implementation☆810Updated 3 months ago
- This is a repository containing solutions to the problem statements given in HDL Bits website.☆353Updated last year
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆353Updated last year
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆128Updated last year
- Verilog AXI components for FPGA implementation☆1,746Updated 3 months ago
- A DDR3 memory controller in Verilog for various FPGAs☆479Updated 3 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,310Updated this week
- Verilog UART☆492Updated 3 months ago
- Awesome ASIC design verification☆307Updated 3 years ago
- Contains the code examples from The UVM Primer Book sorted by chapters.☆546Updated 3 years ago
- Various HDL (Verilog) IP Cores☆813Updated 3 years ago
- Verilog I2C interface for FPGA implementation☆623Updated 3 months ago
- 100 Days of RTL☆368Updated 10 months ago
- training labs and examples☆424Updated 2 years ago
- ☆270Updated last year
- AMBA AXI VIP☆405Updated 11 months ago
- Image Processing Toolbox in Verilog using Basys3 FPGA☆203Updated last month
- Must-have verilog systemverilog modules☆1,797Updated 2 months ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆581Updated 7 years ago
- Common SystemVerilog components☆629Updated last week
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆207Updated last year
- HDLBits website practices & solutions☆739Updated last year
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆149Updated 4 years ago
- Reference examples and short projects using UVM Methodology☆273Updated 3 years ago
- synthesiseable ieee 754 floating point library in verilog☆645Updated 2 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆127Updated 4 years ago
- 使用Verilog实现的CNN模块,可以方便的在FPGA项目中使用☆562Updated 7 years ago
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆202Updated last year