Alternatives and similar repositories for Project-Zipline

Users that are interested in Project-Zipline are comparing it to the libraries listed below

• os-fpga / 1st-CLaaS
  Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications
  ☆205Updated 2 weeks ago
• westerndigitalcorporation / swerv-ISS
  Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator
  ☆202Updated 4 years ago
• vmware-archive / cascade
  A Just-In-Time Compiler for Verilog from VMware Research
  ☆447Updated 4 years ago
• awslabs / aws-fpga-app-notes
  Application notes for the F1 EC2 Instance
  ☆89Updated 4 years ago
• westerndigitalcorporation / omnixtend
  An open standard Cache Coherent Fabric Interface repository
  ☆66Updated 5 years ago
• OFS / opae-sdk
  Open Programmable Acceleration Engine
  ☆266Updated 2 months ago
• openpower-cores / a2i
  ☆248Updated 3 years ago
• Xilinx / Applications
  ☆68Updated 4 years ago
• OPAE / intel-fpga-bbb
  Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
  ☆104Updated 8 months ago
• openpower-cores / a2o
  ☆141Updated 3 years ago
• stevehoover / warp-v
  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  ☆240Updated 4 months ago
• cambridgehackers / connectal
  Connectal is a framework for software-driven hardware development.
  ☆174Updated last year
• open-power / snap
  CAPI SNAP Framework Hardware and Software
  ☆110Updated 4 years ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆226Updated last year
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆869Updated 5 years ago
• LBL-CoDEx / OpenSoCFabric
  OpenSoC Fabric - A Network-On-Chip Generator
  ☆172Updated 5 years ago
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆180Updated this week
• stanford-ppl / spatial
  Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"
  ☆284Updated last year
• cornell-brg / pymtl
  Python-based hardware modeling framework
  ☆244Updated 5 years ago
• Xilinx / HLS
  Vitis HLS LLVM source code and examples
  ☆395Updated last week
• hpcn-uam / Limago
  Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack
  ☆132Updated 4 years ago
• NetFPGA / netfpga
  NetFPGA 1G infrastructure and gateware
  ☆379Updated 6 years ago
• Xilinx / SDAccel_Examples
  SDAccel Examples
  ☆359Updated 3 years ago
• bu-icsg / dana
  Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
  ☆214Updated 5 years ago
• fpgasystems / caribou
  Caribou: Distributed Smart Storage built with FPGAs
  ☆67Updated 7 years ago
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆101Updated 5 years ago
• riscvarchive / riscv-wiki
  ☆248Updated 8 years ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆159Updated 3 years ago
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆55Updated 8 years ago
• OpenCAPI / oc-accel
  OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology
  ☆71Updated last year