hamsternz / simple-riscvLinks
A simple three-stage RISC-V CPU
☆24Updated 4 years ago
Alternatives and similar repositories for simple-riscv
Users that are interested in simple-riscv are comparing it to the libraries listed below
Sorting:
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- LunaPnR is a place and router for integrated circuits☆47Updated 2 months ago
- Wishbone interconnect utilities☆42Updated 8 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆107Updated last month
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆99Updated this week
- Naive Educational RISC V processor☆89Updated last week
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- Reusable Verilog 2005 components for FPGA designs☆47Updated 7 months ago
- Open-source high performance AXI4-based HyperRAM memory controller☆79Updated 3 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆46Updated 3 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- TCP/IP controlled VPI JTAG Interface.☆67Updated 9 months ago
- Spen's Official OpenOCD Mirror☆50Updated 7 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 3 months ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆80Updated 5 years ago
- RISC-V Nox core☆68Updated 2 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated 11 months ago
- Another tiny RISC-V implementation☆59Updated 4 years ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆52Updated last year
- Flip flop setup, hold & metastability explorer tool☆51Updated 2 years ago
- ☆60Updated 4 years ago
- SoftCPU/SoC engine-V☆55Updated 7 months ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 10 months ago
- A set of Wishbone Controlled SPI Flash Controllers☆90Updated 2 years ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board☆31Updated 4 years ago
- Yet Another RISC-V Implementation☆98Updated last year
- ☆39Updated 4 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago