hamsternz / simple-riscvLinks
A simple three-stage RISC-V CPU
☆25Updated 4 years ago
Alternatives and similar repositories for simple-riscv
Users that are interested in simple-riscv are comparing it to the libraries listed below
Sorting:
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- Wishbone interconnect utilities☆44Updated last month
- TCP/IP controlled VPI JTAG Interface.☆69Updated last year
- Spen's Official OpenOCD Mirror☆51Updated 10 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Updated last month
- Reusable Verilog 2005 components for FPGA designs☆49Updated last month
- LunaPnR is a place and router for integrated circuits☆47Updated 6 months ago
- Open-source high performance AXI4-based HyperRAM memory controller☆82Updated 3 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆110Updated last week
- RISC-V Nox core☆71Updated 6 months ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆71Updated 3 years ago
- ☆40Updated 2 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- FuseSoC standard core library☆151Updated last month
- Wishbone to AXI bridge (VHDL)☆44Updated 6 years ago
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆72Updated 7 years ago
- Open source ISS and logic RISC-V 32 bit project☆60Updated last week
- Quick'n'dirty FuseSoC+cocotb example☆19Updated last year
- Naive Educational RISC V processor☆94Updated 3 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆53Updated last year
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆26Updated 6 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 6 months ago
- UNSUPPORTED INTERNAL toolchain builds☆47Updated 2 months ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a log…☆69Updated 4 months ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆83Updated 5 years ago
- A simple DDR3 memory controller☆61Updated 3 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆49Updated 3 years ago