A simple three-stage RISC-V CPU
☆25May 4, 2021Updated 5 years ago
Alternatives and similar repositories for simple-riscv
Users that are interested in simple-riscv are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A very simple RISC-V ISA emulator.☆40Dec 12, 2020Updated 5 years ago
- A customized RISCV core made using verilog☆18Mar 4, 2021Updated 5 years ago
- ☆17Feb 9, 2023Updated 3 years ago
- Connect to your VHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> cosim_jtag <-VHPI or FLI-> VHDL simulator.☆15Dec 30, 2025Updated 8 months ago
- JPEG Compression RTL implementation☆11Aug 19, 2017Updated 9 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instr…☆12Jan 24, 2022Updated 4 years ago
- ☆22Sep 26, 2025Updated 11 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆112Sep 18, 2021Updated 4 years ago
- GDB server to debug CPU simulation waveform traces☆44Feb 21, 2022Updated 4 years ago
- A re-creation of a Cosmac ELF computer, Coded in SpinalHDL☆43Apr 23, 2021Updated 5 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Feb 24, 2023Updated 3 years ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆128Oct 13, 2020Updated 5 years ago
- An in-development lookatme extension that uses ueberzug and urwid_ueberzogen to add image rendering support☆16Oct 2, 2022Updated 3 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆35Dec 10, 2021Updated 4 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- SAT-based ATPG using TG-Pro model☆20Jun 5, 2018Updated 8 years ago
- Implementation of JPEG Compression on an FPGA☆19May 10, 2017Updated 9 years ago
- Instant Neural Graphics Primitives from scratch, zero dependencies. Learning by doing.☆10Aug 18, 2023Updated 3 years ago
- jmp - search files and jump to matching lines in a text editor☆13Apr 3, 2026Updated 5 months ago
- This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…☆15Oct 18, 2021Updated 4 years ago
- LunaPnR is a place and router for integrated circuits☆47Feb 11, 2026Updated 6 months ago
- RV32I single cycle simulation on open-source software Logisim.☆23Oct 8, 2022Updated 3 years ago
- ☆65Nov 9, 2021Updated 4 years ago
- Mini CPU design with JTAG UART support☆21Jun 8, 2021Updated 5 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆28Nov 3, 2020Updated 5 years ago
- ☆10Aug 27, 2026Updated last week
- ☆16Aug 15, 2021Updated 5 years ago
- Wishbone bridge over SPI☆11Nov 13, 2019Updated 6 years ago
- ☆11Nov 21, 2022Updated 3 years ago
- Top level for the November shuttle☆12Nov 20, 2021Updated 4 years ago
- Verilog code for a low power RFID chip that will communicate with I2C sensors.☆13Apr 18, 2014Updated 12 years ago
- [WIP] A C++17 library for language servers☆20May 25, 2020Updated 6 years ago
- Portable high-level assembler with authentic C syntax☆25Jul 1, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Apr 11, 2023Updated 3 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Dec 3, 2025Updated 9 months ago
- A plain VHDL implementation of a small microprocessor fully compatible with the ISA of the well known PicoBlaze by Ken Chapman.☆23Jun 6, 2021Updated 5 years ago
- ☆10Aug 25, 2022Updated 4 years ago
- An Open Source Link Protocol and Controller☆29Aug 1, 2021Updated 5 years ago
- Test that a Perl 6 project has a good and proper META file☆10Jul 4, 2023Updated 3 years ago
- Raku plugin for the asdf version manager.☆12Jan 1, 2023Updated 3 years ago