mesham / pynq_api
C API drivers for PYNQ FPGA board
☆31Updated last year
Related projects ⓘ
Alternatives and complementary repositories for pynq_api
- ☆71Updated 11 months ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆65Updated 3 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆83Updated 4 years ago
- PYNQ Composabe Overlays☆67Updated 5 months ago
- CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture☆124Updated 2 weeks ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆63Updated last year
- ☆83Updated 5 months ago
- PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform☆67Updated 4 years ago
- This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.☆80Updated last year
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆156Updated this week
- IC implementation of Systolic Array for TPU☆153Updated last month
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆59Updated last month
- ☆60Updated 5 years ago
- MulApprox - A comprehensive library of state-of-the-art approximate multipliers☆20Updated 3 years ago
- Convolutional Neural Network Using High Level Synthesis☆83Updated 4 years ago
- AMD University Program HLS tutorial☆63Updated 3 weeks ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆48Updated 5 months ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆129Updated 4 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆71Updated 5 years ago
- IC implementation of TPU☆86Updated 4 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆127Updated 5 months ago
- Verilog implementation of Softmax function☆48Updated 2 years ago
- ☆93Updated 4 years ago
- Vitis HLS Library for FINN☆181Updated last week
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆121Updated last year
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆56Updated 4 years ago
- A collection of research papers on SRAM-based compute-in-memory architectures.☆22Updated last year
- Xilinx AXI VIP example of use☆32Updated 3 years ago
- FFT generator using Chisel☆56Updated 3 years ago
- A collection of tutorials for the fpgaConvNet framework.☆32Updated 2 months ago