mesham / pynq_apiLinks
C API drivers for PYNQ FPGA board
☆41Updated 3 months ago
Alternatives and similar repositories for pynq_api
Users that are interested in pynq_api are comparing it to the libraries listed below
Sorting:
- ☆104Updated 2 years ago
- AMD University Program HLS tutorial☆124Updated last year
- Dataflow QNN inference accelerator examples on FPGAs☆241Updated 4 months ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆102Updated last week
- DPU on PYNQ☆238Updated 5 months ago
- ☆54Updated 6 years ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆41Updated last year
- Vitis HLS Library for FINN☆213Updated last week
- This is a verilog implementation of 4x4 systolic array multiplier☆72Updated 5 years ago
- Verilog implementation of Softmax function☆77Updated 3 years ago
- RISC-V Integration for PYNQ☆180Updated 6 years ago
- This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.☆85Updated 2 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆177Updated 5 months ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆177Updated last year
- Train and deploy LUT-based neural networks on FPGAs☆106Updated last year
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆114Updated 5 years ago
- An AXI4 crossbar implementation in SystemVerilog☆203Updated 4 months ago
- AMD Xilinx University Program Embedded tutorial☆43Updated 2 years ago
- Convolutional Neural Network Using High Level Synthesis☆90Updated 5 years ago
- PYNQ Composabe Overlays☆74Updated last year
- IEEE 754 floating point unit in Verilog☆149Updated 9 years ago
- Library of approximate arithmetic circuits☆61Updated 3 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆98Updated 6 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆141Updated 7 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆178Updated 6 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆185Updated last year
- IC implementation of Systolic Array for TPU☆324Updated last year
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆168Updated 2 years ago
- IC implementation of TPU☆144Updated 6 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago