merledu / Google-Summer-of-CodeLinks
Project ideas list for Google Summer of Code.
☆15Updated 5 months ago
Alternatives and similar repositories for Google-Summer-of-Code
Users that are interested in Google-Summer-of-Code are comparing it to the libraries listed below
Sorting:
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆102Updated 2 months ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆27Updated 3 years ago
- SRAM☆22Updated 4 years ago
- An overview of TL-Verilog resources and projects☆81Updated 3 months ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆43Updated 3 years ago
- Curriculum for a university course to teach chip design using open source EDA tools☆94Updated last year
- Complete tutorial code.☆21Updated last year
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆38Updated 3 years ago
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆59Updated 11 months ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆15Updated 2 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆70Updated 4 years ago
- BlackParrot on Zynq☆43Updated 4 months ago
- Introductory course into static timing analysis (STA).☆94Updated last week
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆73Updated 4 years ago
- ☆24Updated 8 months ago
- ☆16Updated 2 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆85Updated last month
- ☆41Updated 3 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆61Updated last year
- ☆27Updated last week
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated 6 months ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Updated last year
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆83Updated 2 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆71Updated 2 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆59Updated 8 months ago
- Implementing Different Adder Structures in Verilog☆70Updated 5 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆29Updated 3 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆120Updated this week
- RTL data structure☆51Updated 3 weeks ago