merledu / Google-Summer-of-Code
Project ideas list for Google Summer of Code.
☆11Updated 9 months ago
Related projects ⓘ
Alternatives and complementary repositories for Google-Summer-of-Code
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆26Updated last year
- ☆16Updated last year
- ☆10Updated 3 months ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆34Updated 2 years ago
- Complete tutorial code.☆12Updated 6 months ago
- This repo contain the PY-UVM Framework for different RISC-V Cores☆31Updated last year
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆63Updated 3 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆27Updated 2 years ago
- ☆39Updated 2 years ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆35Updated 5 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆62Updated 3 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆69Updated last year
- SRAM☆20Updated 4 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆36Updated 3 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- ☆22Updated 8 months ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆13Updated last year
- Implementing Different Adder Structures in Verilog☆61Updated 5 years ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆13Updated 3 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 3 years ago
- The memory model was leveraged from micron.☆19Updated 6 years ago
- Repository gathering basic modules for CDC purpose☆50Updated 4 years ago
- This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit☆18Updated 6 years ago
- ☆52Updated last year
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆48Updated 2 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆26Updated 2 years ago
- System Verilog BootCamp☆22Updated 2 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆37Updated 3 years ago
- Design and UVM-TB of RISC -V Microprocessor☆13Updated 4 months ago
- Open source ISS and logic RISC-V 32 bit project☆40Updated this week