sfmth / ibnalhaythamLinks
32-bit RISC-V based processor with memory controler
☆16Updated 3 years ago
Alternatives and similar repositories for ibnalhaytham
Users that are interested in ibnalhaytham are comparing it to the libraries listed below
Sorting:
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 4 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆35Updated 11 months ago
- Wishbone interconnect utilities☆44Updated last month
- Quick'n'dirty FuseSoC+cocotb example☆19Updated last year
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆22Updated 2 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆83Updated 5 years ago
- ☆72Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 3 years ago
- Flip flop setup, hold & metastability explorer tool☆52Updated 3 years ago
- Analog and power building blocks for sky130 pdk☆22Updated 4 years ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Updated last year
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆58Updated 2 months ago
- CologneChip GateMate FPGA Module: GMM-7550☆27Updated 2 weeks ago
- TinyTapeout-01 submission repo☆32Updated 3 years ago
- A Risc-V SoC for Tiny Tapeout☆46Updated last month
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆110Updated last week
- Minimal DVI / HDMI Framebuffer☆83Updated 5 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆56Updated 2 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 4 years ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆47Updated last year
- Zero to ASIC group submission for MPW2☆13Updated 10 months ago
- Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board☆23Updated 4 years ago
- an inverter drawn in magic with makefile to simulate☆27Updated 3 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- Set up your GitHub Actions workflow with a OSS CAD Suite☆16Updated last year
- ☆20Updated 5 years ago
- ☆26Updated 4 months ago
- Using VexRiscv without installing Scala☆39Updated 4 years ago