Alternatives and similar repositories for riscv-smol-linux-kernel:

Users that are interested in riscv-smol-linux-kernel are comparing it to the libraries listed below

• rob-ng15 / Silice-Playground
  Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice
  ☆35Updated last year
• tommythorn / tinytapeout-4-bit-cpu
  A design for TinyTapeout
  ☆15Updated 2 years ago
• tomverbeure / ecp5_jtag
  Use ECP5 JTAG port to interact with user design
  ☆26Updated 3 years ago
• ultraembedded / librtos
  Very basic real time operating system for embedded systems...
  ☆16Updated 4 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆40Updated last month
• lxp32 / lxp32-cpu
  A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
  ☆60Updated 3 months ago
• tomverbeure / jtag_uart_example
  Mini CPU design with JTAG UART support
  ☆19Updated 3 years ago
• ulixxe / usb_dfu
  Full Speed USB DFU interface for FPGA and ASIC designs
  ☆17Updated last year
• ZiyangYE / General-Slow-DDR3-Interface
  A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.
  ☆38Updated 10 months ago
• Wren6991 / TwoWireDebug
  Yet Another Debug Transport
  ☆20Updated 2 years ago
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆61Updated 6 years ago
• whitequark / bfcpu2
  A pipelined brainfuck softcore in Verilog
  ☆18Updated 10 years ago
• fontamsoc / pu32
  ☆15Updated last year
• hdl-util / vga-text-mode
  VGA-compatible text mode functionality
  ☆16Updated 4 years ago
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆59Updated 3 weeks ago
• mkvenkit / ulx3s_examples
  Beginner-friendly Verilog based examples for the ULX3S FPGA board.
  ☆11Updated 2 years ago
• mmicko / prjtang
  Documenting the Anlogic FPGA bit-stream format.
  ☆86Updated 2 years ago
• gregdavill / litex-hyperram
  Standard HyperRAM core for ECP5 written in Litex/Migen
  ☆14Updated 5 years ago
• mmicko / cross-fpga
  Cross compile FPGA tools
  ☆22Updated 4 years ago
• mattvenn / ws2812-core
  verilog core for ws2812 leds
  ☆32Updated 3 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆37Updated 3 years ago
• mattvenn / vga_clock_pcb
  Open source hardware down to the chip level!
  ☆30Updated 3 years ago
• dan-rodrigues / pico-hx
  PCB combining Raspberry Pi Pico and iCE40 FPGA
  ☆32Updated 10 months ago
• sylefeb / Silixel
  Exploring gate level simulation
  ☆56Updated 2 years ago
• hamsternz / emulate-risc-v
  A very simple RISC-V ISA emulator.
  ☆37Updated 4 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆56Updated 3 weeks ago
• lawrie / ulx3s_examples
  Example Verilog code for Ulx3s
  ☆40Updated 2 years ago
• lawrie / ulx3s_cores
  Information on cores available on the Ulx3s ECP5 FPGA board
  ☆14Updated 4 years ago
• mattvenn / fpga-sram
  mystorm sram test
  ☆27Updated 7 years ago
• sylefeb / Iron
  Iron: selectively turn RISC-V binaries into hardware
  ☆23Updated last year