Alternatives and similar repositories for hififo:

Users that are interested in hififo are comparing it to the libraries listed below

• ultraembedded / core_mmc
  MMC (and derivative standards) host controller
  ☆23Updated 4 years ago
• HarmonInstruments / verilog
  ☆20Updated 2 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆31Updated 3 years ago
• paulscherrerinstitute / xvcSupport
  ☆17Updated 4 years ago
• lnls-dig / dsp-cores
  Repository containing the DSP gateware cores
  ☆12Updated 5 months ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆22Updated last year
• Bucknalla / ip_cores
  Verilog IP Cores & Tests
  ☆13Updated 6 years ago
• KutuSystems / XilinxIP
  Xilinx IP repository
  ☆13Updated 6 years ago
• hukenovs / adc_configurator
  ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)
  ☆12Updated 6 years ago
• openXC7 / xc7k325t-blinky-nextpnr
  ☆44Updated 2 years ago
• ultraembedded / core_ulpi_wrapper
  ULPI Link Wrapper (USB Phy Interface)
  ☆25Updated 4 years ago
• fcayci / vhdl-axis-uart
  UART to AXI Stream interface written in VHDL
  ☆16Updated 2 years ago
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆20Updated last week
• BrianHGinc / Verilog-Floating-Point-Clock-Divider
  Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…
  ☆14Updated 3 weeks ago
• hVHDL / hVHDL_example_project
  An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…
  ☆26Updated last month
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆38Updated 3 weeks ago
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 8 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆30Updated this week
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆41Updated 4 years ago
• wyvernSemi / mem_model
  High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
  ☆22Updated 3 months ago
• defparam / PCI2Nano-RTL
  An open source FPGA PCI core & 8250-Compatible PCI UART core
  ☆40Updated 4 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆17Updated last year
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆27Updated 9 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆25Updated 3 years ago
• CospanDesign / nysa-sdio-device
  SDIO Device Verilog Core
  ☆22Updated 6 years ago
• fpgadeveloper / ethernet-fmc-processorless
  Example designs for using Ethernet FMC without a processor (ie. state machine based)
  ☆28Updated 3 months ago
• patocarr / axi-traffic-gen
  File editor for the Xilinx AXI Traffic Generator IP
  ☆15Updated 3 months ago
• FarisHijazi / LZ4-Decompressor-Verilog
  Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language
  ☆14Updated 6 years ago
• lnls-dig / general-cores
  general-cores
  ☆18Updated 5 months ago
• analogdevicesinc / testbenches
  Testbenches for HDL projects
  ☆12Updated this week