HarmonInstruments / hififo

Related projects: ⓘ

• ultraembedded / core_ftdi_bridge
  FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge
  ☆26Updated 3 years ago
• ultraembedded / core_mmc
  MMC (and derivative standards) host controller
  ☆22Updated 4 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆21Updated 9 months ago
• HarmonInstruments / verilog
  ☆19Updated 2 years ago
• hukenovs / adc_configurator
  ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)
  ☆11Updated 6 years ago
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆18Updated last month
• mattvenn / logLUTs
  Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.
  ☆19Updated 10 months ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆34Updated 3 months ago
• shalan / Chameleon_SoC
  AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...
  ☆12Updated 3 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆38Updated 4 years ago
• ultraembedded / core_ulpi_wrapper
  ULPI Link Wrapper (USB Phy Interface)
  ☆21Updated 4 years ago
• paulscherrerinstitute / xvcSupport
  ☆17Updated 3 years ago
• KutuSystems / XilinxIP
  Xilinx IP repository
  ☆13Updated 6 years ago
• ericgineer / CIC
  A CIC filter implemented in Verilog
  ☆20Updated 9 years ago
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆32Updated 5 years ago
• lnls-dig / general-cores
  general-cores
  ☆17Updated 8 months ago
• patocarr / axi-traffic-gen
  File editor for the Xilinx AXI Traffic Generator IP
  ☆14Updated last year
• ZiyangYE / General-Slow-DDR3-Interface
  A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.
  ☆35Updated 4 months ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆28Updated 3 years ago
• lewiz-support / LMAC_CORE1
  LMAC Core1 - Ethernet 1G/100M/10M
  ☆16Updated last year
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆17Updated last year
• defparam / PCI2Nano-RTL
  An open source FPGA PCI core & 8250-Compatible PCI UART core
  ☆38Updated 3 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆24Updated 2 years ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆47Updated 2 weeks ago
• enjoy-digital / litesata_axiom
  ☆12Updated 3 years ago
• ultraembedded / core_usb_uart
  USB serial device (CDC-ACM)
  ☆31Updated 4 years ago
• openXC7 / xc7k325t-blinky-nextpnr
  ☆42Updated last year
• hVHDL / hVHDL_example_project
  An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…
  ☆24Updated 2 months ago
• julianfl0w / openStreamHDL
  VHDL Code for infrastructural blocks (designed for FPGA)
  ☆12Updated last year
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 8 years ago