malkadi / FGPU_IPython
☆23Updated 6 years ago
Alternatives and similar repositories for FGPU_IPython:
Users that are interested in FGPU_IPython are comparing it to the libraries listed below
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- This repo is for ECE44x (Fall2015-Spring2016)☆19Updated 7 years ago
- ☆83Updated 4 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆47Updated 8 years ago
- Verilog library for implementing neural networks.☆26Updated 10 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆63Updated last month
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- Caffe to VHDL☆67Updated 4 years ago
- Premade bitstreams and block designs to complemented the PYNQ overlay tutorial☆40Updated 3 years ago
- Support for Rocket Chip on Zynq FPGAs☆40Updated 5 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- RISC-V GPGPU☆34Updated 5 years ago
- ☆65Updated 2 years ago
- ☆85Updated 2 years ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- Generic FIFO implementation with optional FWFT☆56Updated 4 years ago
- verilog CNN generator for FPGA☆34Updated 4 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆133Updated 6 months ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 4 years ago
- A discussion group on Open Source Deep Learning Accelerator, with technical reports and potential hardware/software issues.☆15Updated 7 years ago
- Pulp virtual platform☆23Updated 2 years ago
- Tutorials on HLS Design☆51Updated 5 years ago
- Next generation CGRA generator☆109Updated this week
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆34Updated 5 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆104Updated 6 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆87Updated 5 years ago
- ☆53Updated 4 years ago
- Parallel Array of Simple Cores. Multicore processor.☆95Updated 5 years ago
- Xilinx Deep Learning IP☆92Updated 3 years ago