thinkoco / de10-nano-riscvLinks
A RISC-V SoC ( Hbird e203 ) on Terasic DE10-Nano
☆40Updated 5 years ago
Alternatives and similar repositories for de10-nano-riscv
Users that are interested in de10-nano-riscv are comparing it to the libraries listed below
Sorting:
- 5-stage RISC-V CPU, originally developed for RISCBoy☆35Updated 2 years ago
- A Full Hardware Real-Time Ray-Tracer☆111Updated 2 months ago
- Another tiny RISC-V implementation☆64Updated 4 years ago
- SoftCPU/SoC engine-V☆55Updated 10 months ago
- Exploring gate level simulation☆58Updated 9 months ago
- ULX3S FPGA, RISC-V, ESP32 toolchain installer scripts☆39Updated 5 years ago
- Example Verilog code for Ulx3s☆41Updated 3 years ago
- 😎 A curated list of awesome RISC-V implementations☆142Updated 2 years ago
- HDMI core in Chisel HDL☆53Updated last year
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆82Updated 5 years ago
- CoreScore☆171Updated 2 months ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆47Updated last month
- A pipelined RISC-V processor☆63Updated 2 years ago
- A tiny POWER Open ISA soft processor written in Chisel☆113Updated 2 years ago
- Reusable Verilog 2005 components for FPGA designs☆49Updated last month
- Small footprint and configurable Inter-Chip communication cores☆66Updated 2 weeks ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 4 years ago
- FPGA 101 - Workshop materials☆78Updated 6 years ago
- Graphics demos☆111Updated last year
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆65Updated 8 months ago
- Demo SoC for SiliconCompiler.☆62Updated this week
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)☆34Updated 4 years ago
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆91Updated 7 months ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆76Updated 6 years ago
- Unofficial Yosys WebAssembly packages☆76Updated this week
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆93Updated 7 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆71Updated 3 years ago
- FPGA GPU design for DE1-SoC☆73Updated 4 years ago
- Example projects/code for the OrangeCrab☆108Updated last year
- Using VexRiscv without installing Scala☆39Updated 4 years ago