Alternatives and similar repositories for de10-nano-riscv

Users that are interested in de10-nano-riscv are comparing it to the libraries listed below

• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆58Updated 4 years ago
• Wren6991 / Hazard5
  5-stage RISC-V CPU, originally developed for RISCBoy
  ☆32Updated 2 years ago
• antonblanchard / chiselwatt
  A tiny POWER Open ISA soft processor written in Chisel
  ☆110Updated 2 years ago
• tomverbeure / rt
  A Full Hardware Real-Time Ray-Tracer
  ☆108Updated 2 years ago
• suarezvictor / CflexHDL
  Design digital circuits in C. Simulate really fast with a regular compiler.
  ☆174Updated 2 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 3 years ago
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆95Updated 3 years ago
• JulianKemmerer / PipelineC-Graphics
  Graphics demos
  ☆110Updated last year
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆53Updated 6 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆46Updated 6 months ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 5 months ago
• Martoni / HdmiCore
  HDMI core in Chisel HDL
  ☆51Updated last year
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆169Updated 4 years ago
• lawrie / ulx3s_examples
  Example Verilog code for Ulx3s
  ☆41Updated 3 years ago
• dan-rodrigues / icestation-32
  Compact FPGA game console
  ☆166Updated last year
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆70Updated 3 years ago
• lxp32 / lxp32-cpu
  A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
  ☆62Updated 3 months ago
• mrisc32 / mc1
  A computer (FPGA SoC) based on the MRISC32-A1 CPU
  ☆55Updated last year
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆60Updated last week
• olofk / corescore
  CoreScore
  ☆162Updated 2 weeks ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆57Updated last year
• j-core / jcore-cpu
  J-Core J2/J32 5 stage pipeline CPU core
  ☆53Updated 4 years ago
• projf / fpgatools
  Tools for FPGA development.
  ☆48Updated 3 weeks ago
• laforest / Octavo
  Verilog FPGA Parts Library. Old Octavo soft-CPU project.
  ☆75Updated 6 years ago
• lcbcFoo / ReonV
  ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…
  ☆77Updated 2 years ago
• mmicko / fpga101-workshop
  FPGA 101 - Workshop materials
  ☆76Updated 6 years ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 3 years ago
• aniketnk / circular-queue-verilog
  Implementation of a circular queue in hardware using verilog.
  ☆17Updated 6 years ago
• leos313 / DOOM_FPGA
  Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs
  ☆18Updated 5 years ago
• zxmarcos / huedeon-gpu
  FPGA GPU design for DE1-SoC
  ☆74Updated 3 years ago