RobertBaruch / riscv-reboot
☆42Updated 4 years ago
Alternatives and similar repositories for riscv-reboot:
Users that are interested in riscv-reboot are comparing it to the libraries listed below
- Graded exercises for nMigen (WIP)☆56Updated 4 years ago
- Glacial - microcoded RISC-V core designed for low FPGA resource utilization☆84Updated 5 years ago
- ☆64Updated last year
- Example projects/code for the OrangeCrab☆106Updated 11 months ago
- List of all links you can try with ULX3S☆98Updated 3 years ago
- This repository contains small example designs that can be used with the open source icestorm flow.☆147Updated 3 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 2 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆86Updated 6 years ago
- CoreScore☆148Updated 2 months ago
- The Critical Path - a rambly FPGA blog☆49Updated 4 years ago
- USB Serial on the TinyFPGA BX☆136Updated 3 years ago
- Documenting Lattice's 28nm FPGA parts☆142Updated last year
- A reimplementation of a tiny stack CPU☆82Updated last year
- Board definitions for Amaranth HDL☆112Updated 2 weeks ago
- An Open Source configuration of the Arty platform☆129Updated last year
- Featherweight RISC-V implementation☆52Updated 3 years ago
- User-friendly explanation of Yosys options☆112Updated 3 years ago
- SoC based on VexRiscv and ICE40 UP5K☆156Updated last month
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker☆98Updated 2 years ago
- Doom classic port to lightweight RISC‑V☆90Updated 2 years ago
- Building a RISC-V processor out of LSI logic☆90Updated 4 years ago
- Example LED blinking project for your FPGA dev board of choice☆174Updated last month
- A CPU on an FPGA that you can play Zork on☆49Updated 8 years ago
- Miscellaneous ULX3S examples (advanced)☆77Updated last month
- Exploring gate level simulation☆56Updated this week
- PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers☆29Updated 2 weeks ago
- A FPGA core for a simple SDRAM controller.☆118Updated 3 years ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆60Updated 4 months ago
- Documenting the Lattice ECP5 bit-stream format.☆54Updated last year
- A simple GPU on a TinyFPGA BX☆82Updated 6 years ago